Hi Maurizio,
Yes, building all the FPGAs from scratch in a single run takes a long time.
But maybe that's not needed. Let's start with your questions:
- Are you referring to X3xx? I don't know how to build the FW for the
embedded CPU but you should not have to rebuild it unless you're changing
it. That would have no effect on the FPGA contents.
- If you change even one Verilog file that's used by the FPGA then you
need to rerun make and build them all. The actual compilation of the
Verilog files doesn't take very long. It's place and route that takes the
longest, and there's no way to reuse the place-and-route results from
previous runs. This is a big difference between software compilation and
FPGA compilation.
- We compile all the FPGAs regularly as part of our continuous
integration testing.
- We usually build several in parallel, and we will often reuse IP
build products, so it doesn't take as long. I don't have the numbers with
me, but there are so many variables that I don't think our CI build times
would be very meaningful. I would guess most images take about an hour.
- Sorry, I don't know what machine types.
- You can build under Windows, using Cygwin, but I don't usually
recommend it. Sometimes Vivado generates IP file paths that are too long
for Windows. For building under Windows, I would use WSL. But
Ubuntu is the
best option because that's what we do most of our testing with.
A few other thoughts that might be helpful:
- It's not needed to recompile the FPGA images unless you are
customizing the HDL or RFNoC contents. Use uhd_images_downloader to
download the latest shipping images from Ettus.
- The first part of the compile is building the IP, which takes maybe
1-2 hours. This only has to be done once and subsequent builds will re-use
the same IP output products.
- You only need to build the image you plan to use. For example, if
you're using X310_XG, then only build that one by running "make X310_XG".
- FPGA builds don't take advantage of multiple CPUs well, but you can
run multiple FPGA builds in parallel. RAM usually becomes the limiting
factor. With 16 GiB RAM you should be able to build at least two in
parallel (for X3xx images). It depends on which images you want to build.
Thanks,
Wade
On Fri, Mar 18, 2022 at 4:32 AM STEFANI, Maurizio (External) via USRP-users
<usrp-users@lists.ettus.com> wrote:
> HI,
>
> thank you for your help on the past question, showing me the error due to
> wrong Vivado release (I was using the 2019.2 instead of 2019.1).
>
>
>
> Now I tried to recompile all ettus fpga, but the recompile time was
> greater than 6 hours on an Ubuntu virtual machine with 3GHz CPU and 16GB
> RAM.
>
>
>
> Due to the high recompile time, I was thinking to:
>
> - Compile the FW on the internal processors only and download
> just it. Some one give me help about?
>
> - If I need to change the Verilog files (one or more), is there
> a way to compile and download just them or is it necessary to recompile all?
>
> - Furthermore, someone tried to recompile all ettus FPGA (X3xx
> family)?
>
> o How long time to compile?
>
> o Which PC was used?
>
> o Is it possible to porting the FPGA environment under Windows OS?
>
>
>
> Thank you for your help in advance
>
>
>
> Maurizio Stefani
>
>
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