Hi, It looks like you're using Vivado 2019.2, but 2019.1 is expected. With the wrong Vivado version, you'll have IP version problems. Make sure you run "source setupenv.sh" prior to running "make" and make sure it completes successfully. I also suggest running "make cleanall" to clear out any bad IP build products from the previous failed runs before building again.
Thanks, Wade On Tue, Mar 15, 2022, 12:01 PM STEFANI, Maurizio (External) via USRP-users < usrp-users@lists.ettus.com> wrote: > HI, > > we have an ETTUS X310, I need to re-build and load the original FPGA, > > I loaded from repository the relevant file > > The files are in: > > /vhd/uhd-master/uhd-master/fpga/usrp3/top/x300 > > When I run *make*: > > *maurizio.stefani@ubuntux:~/prove/uhd/uhd-master/fpga/usrp3/top/x300$ > <maurizio.stefani@ubuntux:~/prove/uhd/uhd-master/fpga/usrp3/top/x300$> make* > > *make -f Makefile.x300.inc bin NAME=X300_HG ARCH=kintex7 > PART_ID=xc7k325t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 > X300=1 TOP_MODULE=x300 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 > SFP1_10GBE=1 X300=1" DEFAULT_RFNOC_IMAGE_CORE_FILE=x300_rfnoc_image_core.v > DEFAULT_EDGE_FILE=/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/x300_static_router.hex* > > *make[1]: Entering directory > '/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300'* > > *BUILDER: Checking tools...* > > ** GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu)* > > ** Python 3.8.10* > > ** Vivado v2019.2 (64-bit)* > > *========================================================* > > *BUILDER: Building IP ten_gig_eth_pcs_pma* > > *========================================================* > > *BUILDER: Staging IP in build directory...* > > *BUILDER: Reserving IP location: > /home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma* > > *BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...* > > *BUILDER: Building IP...* > > *[00:00:00] Executing command: vivado -mode batch -source > /home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/tools/scripts/viv_generate_ip.tcl > -log ten_gig_eth_pcs_pma.log -nojournal* > > *WARNING: [IP_Flow 19-2162] IP 'ten_gig_eth_pcs_pma' is locked:* > > *CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the > following file is locked: > /home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci* > > *CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the > following file is locked: > /home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci* > > *[00:00:21] Current task: Initialization +++ Current Phase: Starting* > > *[00:00:22] Current task: Initialization +++ Current Phase: Finished* > > *[00:00:22] Executing Tcl: synth_design -top ten_gig_eth_pcs_pma -part > xc7k325tffg900-2 -mode out_of_context* > > *[00:00:22] Starting Synthesis Command* > > *WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products > for Synthesis target. These output products could be required for > synthesis, please generate the output products using the generate_target or > synth_ip command before running synth_design.* > > *WARNING: [IP_Flow 19-2162] IP 'ten_gig_eth_pcs_pma' is locked:* > > *ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources > specified* > > *ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this > command.* > > *ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this > command.* > > *ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this > command.* > > *ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this > command.* > > *ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this > command.* > > *ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this > command.* > > *CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml'* > > *CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml'* > > *CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml'* > > *CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml'* > > *CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml'* > > *ERROR: [Vivado 12-398] No designs are open* > > *ERROR: [Common 17-69] Command failed: * IP definition '10G Ethernet > PCS/PMA (10GBASE-R/KR) (6.0)' for IP 'ten_gig_eth_pcs_pma' (customized with > software release 2019.1) has a different revision in the IP Catalog.* > > *[00:00:24] Current task: Synthesis +++ Current Phase: Starting* > > *[00:00:24] Current task: Synthesis +++ Current Phase: Finished* > > *[00:00:24] Process terminated. Status: Failure* > > > > *========================================================* > > *Warnings: 3* > > *Critical Warnings: 7* > > *Errors: 9* > > > > *BUILDER: Releasing IP location: > /home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma* > > *make[1]: *** > [/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc:41: > /home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] > Error 1* > > *make[1]: Leaving directory > '/home/maurizio.stefani/prove/uhd/uhd-master/fpga/usrp3/top/x300'* > > *make: *** [Makefile:90: X300_HG] Error 2* > > > > Could you help us to understand the problem > > Thank you > > Maurizio Stefani > > > The information in this e-mail is confidential. The contents may not be > disclosed or used by anyone other than the addressee. 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