Hi Dario, In the UHD manual, issue_stream_cmd() can be called from the UHD radio controller as well as several other controllers including an rx_streamer. The typical way to start streaming from UHD is to call this command on the rx_streamer controller, which in turn propagates this command to the DDC controller and ultimately to the Radio controller. I suppose that this architecture allows each block in the graph to get prepared for the stream that is about to start. In the end, it is the Radio that starts that stream. In your case with only Radios and your block, it seems you could call the Radio_Ctrl->issue_stream_cmd() to start the streaming. I believe that this will indeed invoke a register write as you are thinking. Rob
On Mon, Aug 23, 2021 at 2:02 PM Dario Pennisi <da...@iptronix.com> wrote: > Hi Rob, > As I was mentioning we're trying to get rid of the streamers so ideally > I'd only have two radios connected to my block which has no outputs. The > graph would appear to be entirely in the FPGA and nothing except register > reads and writes would enter or exit FPGA. > As far as I understand there is no start streaming command on the radios > and I don't think I have them on my block. > I was tempted to directly write radio stream registers but it's a very > dirty solution... > > Thanks, > > Dario > > Il Lun 23 Ago 2021, 15:48 Rob Kossler <rkoss...@nd.edu> ha scritto: > >> Hi Dario, >> How do you start the streaming? Using issue_stream_cmd()? If so, is this >> called on the streamer object or on the DDC or radio? The reason I ask is >> that if you call it on the streamer, I'm wondering if your issue is related >> to command propagation. That is, the command is not propagating through >> your block. If this is the case, try calling issue_stream_cmd() on the DDC >> block which will then propagate it to the Radio block (or call directly on >> the Radio if there is no DDC). >> Rob >> >> On Fri, Aug 20, 2021 at 1:26 PM Dario Pennisi <da...@iptronix.com> wrote: >> >>> Hi, >>> i'm trying to optimize FPGA consumption and on N310/UHD4.1.0.1 i am >>> testing a block that needs only 2 inputs and no outputs. since i don't need >>> to stream any data in/out of the FPGA i declared a single streamer with >>> control only and declared no connection between it and any block in the yml >>> and this way i can see i can read and write registers. >>> the issue arises when i try to stream data to the block: if i have no >>> outputs declared, inputs will not receive anything. if i have 1 output >>> connected to a streamer, connected to a null sink, i can receive from the >>> first input, if i have 2 outputs connected to two streamers connected to >>> null sinks i can receive on both inputs. >>> is there any way i can get rid of those useless outputs and remove at >>> least 1 endpoint? >>> if i declare i need a single endpoint with no data why does it complain >>> if i don't declare buff_size in the yml? >>> my rfnoc block uses a noc shell that outputs axi stream payload which i >>> adapted for programmable number of inputs and outputs. >>> It seems to me the issue is not on the FPGA side as the backend block >>> seems to properly report information and o don't see any connection in NOC >>> shell between input and outputs other than in there... >>> >>> Thanks, >>> >>> Dario >>> _______________________________________________ >>> USRP-users mailing list -- usrp-users@lists.ettus.com >>> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >>> >>
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