On 08/07/2021 04:26 PM, [email protected] wrote:
Hi, Marcus,
Thanks for your reply. The clear & precise problem description is an
endless pursuit I should try to do better. My experience is a lot of
problem get answered by itself when it is described clear enough to
the very detail, it’s part of a learning process.
My current guess is the FPGA program after JTAG download runs the ZPU
to retrieve the existing settings, such as the IP, from EEPROM. The
page(s) for setting must live outside the pages used for FPGA image,
as the uhd_image_loader process won’t change these settings. This is
another entry in my TODO list.
Wish everybody a nice weekend.
Indeed it was a very deliberate design choice to have the IP addresses
in EEPROM entirely outside of the area for the FPGA. Otherwise, every time
you loaded a new FPGA image (such as you might want to do when doing
your own FPGA work), it would change to whatever (perhaps default)
address was in the FPGA image. You want them to be separately
programmable things.
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