I finally caught the bug, I mistakenly swapped the REF and TRG ports and
one the USRPs couldnt lock to the reference.
Thanks for your support.
On 7/7/21 17:22, Marcus D. Leech wrote:
On 07/07/2021 11:19 AM, Armin Ghani wrote:
I checked the signals at the cable end which attached to the USRP
input reference.
And all the cables are the same part number with same cable length.
Is there anything else to check?
Check each X310 individually to see if this affects only a single X310
reference input or all of them.
If all then there's a clock-quality issue. Like I mentioned the REF
OUT capability on the X310 as never, as far as I recall,
fully-developed.
On 7/7/21 17:16, Marcus D. Leech wrote:
On 07/07/2021 11:14 AM, Armin Ghani wrote:
I've just checked the reference source for all USRPs, both 10MHz
and 1PPS are perfectly distributed on the octoclock output.
10MHz => 3.5V p-p
1PPS => 5V p-p
The next thing to check then is the cabling.
Regards.
On 7/7/21 16:43, Marcus D. Leech wrote:
On 07/07/2021 10:38 AM, Armin Ghani wrote:
What do you mean by not implemented? Do you mean it is not
assembled on USRP hardware?
My recollection is that the "feature" was implemented originally,
but it was found to be a very poor reference clock, and I thought
(maybe I'm wrong) that later FPGA releases ended up turning it off.
So the next thing to check is that 10MHz and 1PPS are actually
making it out of your octoclock (with a scope) when things are
configured (assuming that the input is correct).
Regards.
On 7/7/21 16:33, Marcus D. Leech wrote:
On 07/07/2021 09:36 AM, Armin Ghani wrote:
Dear USRP and GNURadio Community
I have 3 USRP X310 with two SBX-120 daughterboards installed.
each of USRPs has two dedicated 10GB Interface with host server.
I'm trying to build a synchronouse system which has 2 receiver
and one transmitter and Octoclock CDA-2990 is used to synch
both clock and time of all USRPs.
Since the octoclock doesnt provide reference source, I used one
of the USRPs clock source external output as octoclock input
rerefence and three distributed output references (both 10MHz
and PPS) are fed to the three USRPs (including the USRP which
provide reference source to the octoclock)
Attached you can find the flowgraph in GNURadio to run a very
simple system in order to evaluate the results. You can find
more details of how UHD source and sink blocks are configured.
In summary, for the UHD sink block, clock and time references
are set to internal and default respectively. And UHD source
block are configured as multi-usrp config with clock and time
sources for both motherboards to the external.
GNURadio v3.8.2.0 and UHD v3.15.0.0 are used.
When I run the flowgraph, after UHD initialization for all
USRPs, the running system ends up with the folowing output in
console:
Executing: /usr/bin/python3 -u
/home/.../Documents/gnuradio-tests/octoclock_test.py
[INFO] [UHD] linux; GNU C++ version 9.3.0; Boost_107100;
UHD_3.15.0.HEAD-0-gaea0e2de
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 1472 bytes.
[WARNING] [X300] For the 192.168.30.2 connection, UHD
recommends a send frame size of at least 4000 for best
performance, but your configuration will only allow 1472.This
may negatively impact your maximum achievable sample rate.
Check the MTU on the interface and/or the send_frame_size argument.
[WARNING] [X300] For the 192.168.30.2 connection, UHD
recommends a receive frame size of at least 8000 for best
performance, but your configuration will only allow 1472.This
may negatively impact your maximum achievable sample rate.
Check the MTU on the interface and/or the recv_frame_size argument.
[INFO] [X300] Maximum frame size: 1472 bytes.
[WARNING] [X300] For the 192.168.50.2 connection, UHD
recommends a send frame size of at least 4000 for best
performance, but your configuration will only allow 1472.This
may negatively impact your maximum achievable sample rate.
Check the MTU on the interface and/or the send_frame_size argument.
[WARNING] [X300] For the 192.168.50.2 connection, UHD
recommends a receive frame size of at least 8000 for best
performance, but your configuration will only allow 1472.This
may negatively impact your maximum achievable sample rate.
Check the MTU on the interface and/or the recv_frame_size argument.
[INFO] [X300] Radio 1x clock: 200 MHz
[INFO] [X300] Radio 1x clock: 200 MHz
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID:
0xF1F0D00000000000)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1311 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1318 MB/s)
[INFO] [1/DmaFIFO_0] Initializing block control (NOC ID:
0xF1F0D00000000000)https://www.radio-astronomy.org/
[INFO] [1/DmaFIFO_0] BIST passed (Throughput: 1299 MB/s)
[INFO] [1/DmaFIFO_0] BIST passed (Throughput: 1299 MB/s)
[INFO] [0/Radio_0] Initializing block control (NOC ID:
0x12AD100000000001)
[INFO] [1/Radio_0] Initializing block control (NOC ID:
0x12AD100000000001)
[INFO] [0/Radio_1] Initializing block control (NOC ID:
0x12AD100000000001)
[INFO] [1/Radio_1] Initializing block control (NOC ID:
0x12AD100000000001)
[INFO] [0/DDC_0] Initializing block control (NOC ID:
0xDDC0000000000000)
[INFO] [1/DDC_0] Initializing block control (NOC ID:
0xDDC0000000000000)
[INFO] [0/DDC_1] Initializing block control (NOC ID:
0xDDC0000000000000)
[INFO] [1/DDC_1] Initializing block control (NOC ID:
0xDDC0000000000000)
[INFO] [0/DUC_0] Initializing block control (NOC ID:
0xD0C0000000000000)
[INFO] [1/DUC_0] Initializing block control (NOC ID:
0xD0C0000000000000)
[INFO] [0/DUC_1] Initializing block control (NOC ID:
0xD0C0000000000000)
[INFO] [1/DUC_1] Initializing block control (NOC ID:
0xD0C0000000000000)
Traceback (most recent call last):
File "/home/.../Documents/gnuradio-tests/octoclock_test.py",
line 334, in <module>
main()
File "/home/.../Documents/gnuradio-tests/octoclock_test.py",
line 310, in main
tb = top_block_cls()
File "/home/.../Documents/gnuradio-tests/octoclock_test.py",
line 91, in __init__
self.uhd_usrp_source_0.set_clock_source('external', 0)
File
"/usr/local/lib/python3/dist-packages/gnuradio/uhd/uhd_swig.py",
line 3793, in set_clock_source
return _uhd_swig.usrp_source_sptr_set_clock_source(self,
source, mboard)
RuntimeError: RuntimeError: Reference Clock PLL failed to lock
to external source.
--
Armin Ghani
Research Engineer | Communication Systems Division (CSD)
agh...@cttc.es <mailto:agh...@cttc.es>| +34 93 645 29 08 (2143)
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
Av. Carl Friedrich Gauss, 7 - Edifici B4 - PMT
08860 - Castelldefels (Barcelona, Spain)
www.cttc.cat
_______________________________________________
USRP-users mailing list --usrp-users@lists.ettus.com
To unsubscribe send an email tousrp-users-le...@lists.ettus.com
Check to make sure that the REF OUT on the X310 you're using as
the reference is actually producing a 10MHz clock. My recollection
is that the REF OUT on the X310 was never actually implemented.
_______________________________________________
USRP-users mailing list --usrp-users@lists.ettus.com
To unsubscribe send an email tousrp-users-le...@lists.ettus.com
--
Armin Ghani
Research Engineer | Communication Systems Division (CSD)
agh...@cttc.es <mailto:agh...@cttc.es>| +34 93 645 29 08 (2143)
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
Av. Carl Friedrich Gauss, 7 - Edifici B4 - PMT
08860 - Castelldefels (Barcelona, Spain)
www.cttc.cat
--
Armin Ghani
Research Engineer | Communication Systems Division (CSD)
agh...@cttc.es <mailto:agh...@cttc.es>| +34 93 645 29 08 (2143)
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
Av. Carl Friedrich Gauss, 7 - Edifici B4 - PMT
08860 - Castelldefels (Barcelona, Spain)
www.cttc.cat
--
Armin Ghani
Research Engineer | Communication Systems Division (CSD)
agh...@cttc.es <mailto:agh...@cttc.es>| +34 93 645 29 08 (2143)
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
Av. Carl Friedrich Gauss, 7 - Edifici B4 - PMT
08860 - Castelldefels (Barcelona, Spain)
www.cttc.cat
--
Armin Ghani
Research Engineer | Communication Systems Division (CSD)
agh...@cttc.es <mailto:agh...@cttc.es>| +34 93 645 29 08 (2143)
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
Av. Carl Friedrich Gauss, 7 - Edifici B4 - PMT
08860 - Castelldefels (Barcelona, Spain)
www.cttc.cat
_______________________________________________
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-le...@lists.ettus.com
