Hi,
I'm building a new FPGA image for E310 based on the yaml file
"e310_rfnoc_image_core.yml". I'm adding a FFT block per the
instructions in "Getting_Started_with_RFNoC_in_UHD_4.0".
However, when I run:
rfnoc_image_builder -y ./e310_with_fft.yml -t E310
I get the error:
[ERR] 1 unresolved clk domain(s)
[ERR] fft0:ce
[ERR] Please specify the clock(s) to connect
Even though the clk_domains is configured as:
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: ce, dstblk: fft0, dstport:ce }
If I remove the FFT block the compile process begins properly.
Any ideas?
Mike
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