Hi all,
I'm building a setup with three X310 equipped with TwinRX daughterboards
running at full 100MSps. The USRPs are synchronized using the
Octoclock-G. The problem is that I am observing offsets of up to one
sample in both directions across the individual devices (in regards to
channel 0 on USRP1). These offsets only change after re-initialization
of the multi_usrp object or manipulating the timekeeping registers
(set_time_next_pps()) of the devices but they seem to be completely random.
I've looked into the clocking system and it seems like the 200MHz
*radio_clk* should be phase aligned across all devices through the 10MHz
reference input. (The LMK is in 0-delay mode and align_phase is set for
the PLL/MMCM generating the radio_clk in the FPGA image).
The only other source for the offsets I could imagine would be a
miss-alignment of the sample-strobes coming out of the *rx_frontend_gen3
*(more specifically the keep_1_in_2 decimator) because the devices come
out of reset at different times and therefore one USRP could have
produced an even amount of samples while the other an odd amount (-> the
decimators on the individual boards are in different states/counter
values). This would result in offsets in the 200MHz domain of the
baseband samples.
Thanks,
David
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