This is the code for the adder (between dds_timed and axi_wrapper):
assign s_axis_data_tvalid2[0] = s_axis_data_tvalid[1] & s_axis_data_tvalid[0
];
assign s_axis_data_tvalid2[1] = s_axis_data_tvalid[1] & s_axis_data_tvalid[0
];
assign s_axis_data_tuser2 = s_axis_data_tuser;
assign s_axis_data_tlast2[0] = s_axis_data_tlast[0];
assign s_axis_data_tlast2[1] = s_axis_data_tlast[1];
assign s_axis_data_tdata2[15: 0] = s_axis_data_tdata[47:32] +
s_axis_data_tdata[15: 0];
assign s_axis_data_tdata2[31:16] = s_axis_data_tdata[63:48] +
s_axis_data_tdata[31:16];
assign s_axis_data_tready_aux = ~|(~{s_axis_data_tready_out[0
],s_axis_data_tready_out[1]} & 2'b11);
assign s_axis_data_tready[0] = s_axis_data_tvalid[0] & s_axis_data_tvalid[1]
& s_axis_data_tready_aux;
assign s_axis_data_tready[1] = s_axis_data_tvalid[0] & s_axis_data_tvalid[1]
& s_axis_data_tready_aux;
El vie., 10 jul. 2020 a las 11:59, Carlos Alberto Ruiz Naranjo (<
carlosruiznara...@gmail.com>) escribió:
> Hi,
>
> I'm customizing the DUC block to do it 2input:1output
>
> input 0 ---> DUC --->
> add ---> output
> input 1 ---> DUC --->
>
> I have added an addsub module between dds_timed and axi_wrapper.
> Apparently it works fine. I can see two tones in the output if the inputs
> are 2 tones.
>
> But I have a synchronization problem. If input_0 is a sine and input_1 is
> a sine with pi phase the output should be 0. And the output is 0, but after
> a while (3 minutes) no. I think that the channels are out of sync before
> the adder.
>
> Any idea about what is happening?
>
> Thank you :)
>
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
