Dear list,Recently I have updated to master branch of UHD repo and I see that uhd_image_builder has moved to rfnoc_image_builder. Plus, it seems that uhd_image_builder_gui has been deleted in favour of gnuradio-companion > UHD > RFNoC Image Builder (at gnuradio master branch)
However, I only see DDC, DUC, FFT, Radio, Stream Endpoint and X310 Device blocks. Do you know where to find the OOT blocks available 3.15 (siggen, sum, fir filter, gain, etc.)?
Furthermore, is there some mail/doc/something that explains how to use rfnoc_image_builder?
I use./rfnoc_image_builder.py -r /home/phenarejos/Documents/rfnoc_test.grc -F /home/phenarejos/uhd/fpga/ -b /usr/local/share/gnuradio/grc/blocks
but it gives me this error: Traceback (most recent call last): File "./rfnoc_image_builder.py", line 189, in <module> sys.exit(main()) File "./rfnoc_image_builder.py", line 167, in main config, source, device, target = image_config(args) File "./rfnoc_image_builder.py", line 118, in image_config config = image_builder.convert_to_image_config(config, args.grc_blocks)File "/usr/local/lib/python3/dist-packages/uhd/imgbuilder/image_builder.py", line 464, in convert_to_image_config seps = {item["name"]: item for item in grc["blocks"] if item["parameters"]["type"] == 'sep'} File "/usr/local/lib/python3/dist-packages/uhd/imgbuilder/image_builder.py", line 464, in <dictcomp> seps = {item["name"]: item for item in grc["blocks"] if item["parameters"]["type"] == 'sep'}
KeyError: 'type' I also attach the grc file. It is the same example I found here: https://www.gnuradio.org/grcon/grcon19/presentations/uhd_four_o/Martin%20Braun%20-%20UHD%20Four-O.pdf Thank you. -- Dr. Pol Henarejos Senior Researcher Array and Multi-Sensor Processing Department, Communication Systems Division pol.henare...@cttc.cat Centre Tecnològic de Telecomunicacions de Catalunya (CTTC) Av. Carl Friedrich Gauss, 7 08860 Castelldefels, Barcelona (Spain) Tel: +34 93 645 29 00 Ext: 2177 www.cttc.catYour identification data and the data contained in the emails and attached files can be incorporated into our databases, in order to maintain professional and / or commercial relationships, and that it will be preserved throughout the relationship. You can exercise your right to access, rectification, erasure, restriction of processing, to portability and to object by sending an email to d...@cttc.cat. This message and any attached document, where appropriate, may be confidential and intended for the original recipient only.
options: parameters: author: phenarejos catch_exceptions: 'True' category: '[GRC Hier Blocks]' cmake_opt: '' comment: '' copyright: '' description: '' gen_cmake: 'On' gen_linking: dynamic generate_options: qt_gui hier_block_src_path: '.:' id: rfnoc_test max_nouts: '0' output_language: python placement: (0,0) qt_qss_theme: '' realtime_scheduling: '' run: 'True' run_command: '{python} -u {filename}' run_options: prompt sizing_mode: fixed thread_safe_setters: '' title: Not titled yet states: bus_sink: false bus_source: false bus_structure: null coordinate: [8, 8] rotation: 0 state: enabled blocks: - name: samp_rate id: variable parameters: comment: '' value: '32000' states: bus_sink: false bus_source: false bus_structure: null coordinate: [184, 12] rotation: 0 state: enabled - name: uhd_fpga_ddc_0 id: uhd_fpga_ddc parameters: affinity: '' alias: '' comment: '' desc: ddc_2x64.yml maxoutbuf: '0' minoutbuf: '0' nports: '2' type: block states: bus_sink: false bus_source: false bus_structure: null coordinate: [440, 320.0] rotation: 180 state: true - name: uhd_fpga_ddc_1 id: uhd_fpga_ddc parameters: affinity: '' alias: '' comment: '' desc: ddc_2x64.yml maxoutbuf: '0' minoutbuf: '0' nports: '2' type: block states: bus_sink: false bus_source: false bus_structure: null coordinate: [448, 136.0] rotation: 180 state: true - name: uhd_fpga_duc_0 id: uhd_fpga_duc parameters: affinity: '' alias: '' comment: '' desc: duc_2x64.yml maxoutbuf: '0' minoutbuf: '0' nports: '2' type: block states: bus_sink: false bus_source: false bus_structure: null coordinate: [824, 352.0] rotation: 180 state: true - name: uhd_fpga_duc_0_0 id: uhd_fpga_duc parameters: affinity: '' alias: '' comment: '' desc: duc_2x64.yml maxoutbuf: '0' minoutbuf: '0' nports: '2' type: block states: bus_sink: false bus_source: false bus_structure: null coordinate: [824, 168.0] rotation: 180 state: true - name: uhd_fpga_radio_0 id: uhd_fpga_radio parameters: affinity: '' alias: '' comment: '' desc: radio_2x64.yml maxoutbuf: '0' minoutbuf: '0' nports: '2' type: block states: bus_sink: false bus_source: false bus_structure: null coordinate: [656, 88.0] rotation: 180 state: true - name: uhd_fpga_radio_1 id: uhd_fpga_radio parameters: affinity: '' alias: '' comment: '' desc: radio_2x64.yml maxoutbuf: '0' minoutbuf: '0' nports: '2' type: block states: bus_sink: false bus_source: false bus_structure: null coordinate: [656, 272.0] rotation: 180 state: true - name: uhd_fpga_sep_0 id: uhd_fpga_sep parameters: affinity: '' alias: '' buff_size: '32768' comment: '' ctrl: 'True' data: 'True' maxoutbuf: '0' minoutbuf: '0' type: sep states: bus_sink: false bus_source: false bus_structure: null coordinate: [504, 464.0] rotation: 0 state: true - name: uhd_fpga_sep_1 id: uhd_fpga_sep parameters: affinity: '' alias: '' buff_size: '32768' comment: '' ctrl: 'True' data: 'True' maxoutbuf: '0' minoutbuf: '0' type: sep states: bus_sink: false bus_source: false bus_structure: null coordinate: [504, 504.0] rotation: 0 state: true - name: uhd_fpga_sep_2 id: uhd_fpga_sep parameters: affinity: '' alias: '' buff_size: '32768' comment: '' ctrl: 'True' data: 'True' maxoutbuf: '0' minoutbuf: '0' type: sep states: bus_sink: false bus_source: false bus_structure: null coordinate: [520, 8.0] rotation: 0 state: true - name: uhd_fpga_sep_3 id: uhd_fpga_sep parameters: affinity: '' alias: '' buff_size: '32768' comment: '' ctrl: 'True' data: 'True' maxoutbuf: '0' minoutbuf: '0' type: sep states: bus_sink: false bus_source: false bus_structure: null coordinate: [520, 48.0] rotation: 0 state: true - name: uhd_fpga_x310_0 id: uhd_fpga_x310 parameters: affinity: '' alias: '' comment: '' maxoutbuf: '0' minoutbuf: '0' type: device states: bus_sink: false bus_source: false bus_structure: null coordinate: [1032, 176.0] rotation: 180 state: true connections: - [uhd_fpga_ddc_0, port0, uhd_fpga_sep_0, in0] - [uhd_fpga_ddc_0, port1, uhd_fpga_sep_1, in0] - [uhd_fpga_ddc_1, port0, uhd_fpga_sep_2, in0] - [uhd_fpga_ddc_1, port1, uhd_fpga_sep_3, in0] - [uhd_fpga_duc_0, port0, uhd_fpga_radio_1, port0] - [uhd_fpga_duc_0, port1, uhd_fpga_radio_1, port1] - [uhd_fpga_duc_0_0, port0, uhd_fpga_radio_0, port0] - [uhd_fpga_duc_0_0, port1, uhd_fpga_radio_0, port1] - [uhd_fpga_radio_0, ctrl_port, uhd_fpga_x310_0, ctrlport_radio0] - [uhd_fpga_radio_0, port0, uhd_fpga_ddc_1, port0] - [uhd_fpga_radio_0, port1, uhd_fpga_ddc_1, port1] - [uhd_fpga_radio_1, ctrl_port, uhd_fpga_x310_0, ctrlport_radio1] - [uhd_fpga_radio_1, port0, uhd_fpga_ddc_0, port0] - [uhd_fpga_radio_1, port1, uhd_fpga_ddc_0, port1] - [uhd_fpga_sep_0, out0, uhd_fpga_duc_0, port0] - [uhd_fpga_sep_1, out0, uhd_fpga_duc_0, port1] - [uhd_fpga_sep_2, out0, uhd_fpga_duc_0_0, port0] - [uhd_fpga_sep_3, out0, uhd_fpga_duc_0_0, port1] - [uhd_fpga_x310_0, ce, uhd_fpga_ddc_0, ddc] - [uhd_fpga_x310_0, ce, uhd_fpga_ddc_1, ddc] - [uhd_fpga_x310_0, ce, uhd_fpga_duc_0, duc] - [uhd_fpga_x310_0, ce, uhd_fpga_duc_0_0, duc] - [uhd_fpga_x310_0, radio, uhd_fpga_radio_0, radio] - [uhd_fpga_x310_0, radio, uhd_fpga_radio_1, radio] - [uhd_fpga_x310_0, time_keeper, uhd_fpga_radio_0, time_keeper] - [uhd_fpga_x310_0, time_keeper, uhd_fpga_radio_1, time_keeper] - [uhd_fpga_x310_0, x300_radio0, uhd_fpga_radio_0, x300_radio] - [uhd_fpga_x310_0, x300_radio1, uhd_fpga_radio_1, x300_radio] metadata: file_format: 1
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