Hi, I am trying to solve what I think is a timing issue with my RFNOC design. I have an E310 running UHD 3.15LTS/GNUradio 3.7/gr-ettus.
I have created a custom RFNOC block for GNUradio without much custom logic, I've managed to just reuse code blocks from the uhd-fpga repo in lib/rfnoc. In particular, I am using the following blocks in this order: complex to magphase (ISE IP in lib/rfnoc) -> moving_sum -> keep_one_in_n -> fifo with size 5 (so I don't have to have RFNOC:FIFO blocks taking up room in the FPGA). For moving_sum I'm trying to use 511 as the sum length and for keep_one_in_n I am using 512. I have made this block a permanent 2 input/2 output block by setting those parameters in noc_shell instantiation. I am using the axi_wrappers (0 and 1) with SIMPLE MODE set to 0, and simply utilizing the cvita_hdr_modify.v IP exactly as utilized in the noc_block_keep_one_in_n.v block to set the tuser headers. In Vivado behavioral simulation the data correctly flows through but what I am unsure about is the fact that after synthesizing and loading the FPGA bit file into the e310 and running my flowgraph, it just repeatedly prints out timeout on channel 0. By the way this code does work on just a single input/single output application but I want to consolidate it into a single GRC block to save space on the relatively small FPGA. What do I need to do to sync the 2 e310 rx2 channels so they arrive close to on-time in GRC? Or is that probably not the problem? I assume I should be looking at how it's done in noc_block_ddc/duc as they have implemented timed samples within those? Thanks, Andrew
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