EJ, I don't quite understand your comments. I'm talking about Ettus code in the 3.15 release. Rob
On Thu, Jan 30, 2020 at 3:57 PM EJ Kreinar <ejkrei...@gmail.com> wrote: > Whoa there, > > I havent updated any of my code to UHD-3.15 yet so you're a bit ahead of > me! I usually make the relevant PRs if/when OOT build process breaks -- so > I'd recommend sending over the relevant PR to fpga repo? Will probably help > me a few months down the line :P > > Thanks! > EJ > > On Wed, Jan 29, 2020 at 5:28 PM Andrew Payne via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> I had the same issues! I just ended up putting my verilog file paths in >> Makefile.n3xx.inc and it works. This might need to be fixed unless I did >> something wrong. >> >> On Wed, Jan 29, 2020 at 16:18 Rob Kossler via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> I have been struggling all day with why I can't build my OOT rfnoc >>> blocks for the N310 using v3.15.0.0. It appears that the problem is that >>> there is a file top/n3xx/Makefile.srcs that is clearing the RFNOC_OOT_SRCS >>> variable after it is set in the users OOT makefile. I just commented the >>> line in top/n3xx/Makefile.srcs and that seems to do the trick. Is this a >>> known issue? >>> >>> >>> # Makefile.n3xx.inc >>> ... >>> include $(BASE_DIR)/n3xx/Makefile.OOT.inc >>> include $(BASE_DIR)/n3xx/Makefile.srcs >>> ... >>> >>> # Makefile.srcs >>> RFNOC_OOT_SRCS = \ >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >
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