Daniel, The X310 has 1Gb of DRAM available to the FPGA. In the stock images, some of this DRAM is used for FIFOs between RFNoC blocks. If you were to replace these DRAM FIFOs with SRAM (i.e. compile the XGS image for X310), you should theoretically be able to leverage all of the X310s DRAM in the Replay Block by modifying axi_intercon_2x64_128_bd.
Sam Reiter On Wed, Jan 15, 2020 at 2:09 AM Daniel Ozer via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello everyone , > I want to load a file using the replay block that will consume almost all > the space of the ddr3 on the device . > I saw that replay block has a address range of 32mib which is not enough > at all . > How can i change the space address of the replay block and what is the max > size i can put so i want damage other components in the design? > Thank you in advance. > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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