Hi Varban, just a transient observation: your $PATH contains *a lot* of redundant ISE paths, as if some script kept recursively sourcing the xilinx settings. How are these set? Do you have a specific shell that you prepare for synthesis?
Best regards, Marcus On Fri, 2019-12-27 at 12:47 +0000, Varban Metodiev via USRP-users wrote: > Hi, > > I am trying to compile the FPGA image for a b205mini as per the > official instructions. My environment looks like this: > > [ise@localhost b2xxmini]$ which xtclsh > /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh > [ise@localhost b2xxmini]$ pwd > /home/ise/USRP/fpga/usrp3/top/b2xxmini > > [ise@localhost b2xxmini]$ echo $PATH > /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sys > gen/util:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:/opt/Xilinx/14.7/ISE_ > DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xil > inx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microbl > aze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc- > eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/ > 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili > nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X > ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li > n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I > SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx > /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt > /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D > S/EDK/gnu/powerpc- > eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/ > 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili > nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X > ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li > n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I > SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx > /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt > /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D > S/EDK/gnu/powerpc- > eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/ > 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili > nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X > ilinx/14.7/ISE_DS/common/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/li > n64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/I > SE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx > /14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt > /Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_D > S/EDK/gnu/powerpc- > eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/ > 14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xili > nx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/X > ilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt- > 3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin: > /home/ise/bin:/home/ise/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh > > > Upon starting the "make B205mini", the header files inside > /fpga/usrp3/lib/ cannot be accessed. > > INFO:ProjectMgmt - Include file found: > '/home/ise/USRP/fpga/usrp3/lib/wishbone/i2c_master_defines.v' in > file > "/home/ise/USRP/fpga/usrp3/lib/wishbone/i2c_master_byte_ctrl.v" > line 73 > ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy. > WARNING:ProjectMgmt - Circular Reference: > work:Module|cam_priority_encoder > > > > Adding source to project: > > > > /home/ise/USRP/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v > INFO:HDLCompiler:1845 - Analyzing Verilog file > "/home/ise/USRP/fpga/usrp3/lib/packet_proc/source_flow_control.v" > into > library work > ERROR:HDLCompiler:281 - > "/home/ise/USRP/fpga/usrp3/lib/packet_proc/source_flow_control.v" > Line 55: > Cannot open include file "chdr_pkt_types.vh". > INFO:HDLCompiler:1845 - Analyzing Verilog file > "/home/ise/USRP/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v" into > library work > ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy. > WARNING:ProjectMgmt - Circular Reference: > work:Module|cam_priority_encoder > > > > Adding source to project: > > > > /home/ise/USRP/fpga/usrp3/lib/timing/time_compare.v > INFO:TclTasksC - File > "/home/ise/USRP/fpga/usrp3/lib/timing/time_compare.v" is > already present in the project > > May you please advise how add the search path correctly? Or maybe I > have missed something in the environment configuration? > > Regards, > Varban > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
