On 12/09/2019 03:35 PM, Lukas Haase wrote:
Hi Marcus,
Von: "Marcus D. Leech" <patchvonbr...@gmail.com>
On 12/09/2019 03:11 PM, Lukas Haase wrote:
No, I only have one RX channel at the moment.
--> One TX @ f and one RX @ 2f.
The phase relation between this TX+RX should stay constant/coherent once both
TX+RX tune to a different f and back.
Let me know if the setup is clear, otherwise I'll try to draw a block
diagram/equations or I can also send the GRC screenshots.
Thanks,
Luke
You code shows two RX channels:
now = self.uhd_usrp_sink_0.get_time_now()
self.uhd_usrp_sink_0.set_command_time(now + uhd.time_spec(1))
self.uhd_usrp_source_0.set_command_time(now + uhd.time_spec(1))
self.uhd_usrp_source_0.set_center_freq(2*self.fcenter, 0)
self.uhd_usrp_source_0.set_center_freq(2*self.fcenter, 1)
self.uhd_usrp_sink_0.set_center_freq(self.fcenter, 0)
self.uhd_usrp_source_0.clear_command_time()
self.uhd_usrp_sink_0.clear_command_time()
Sorry for the confusion.
You are right, there are 2 RX channels but I only use one of them.
So, you're measuring the phase-offset between the TX side and the RX
side at the 2nd harmonic, and expecting that phase relationship to be
the same across re-tunes?
Yes, this is exactly what I want.
I'm not sure that's possible.
Why not?
Conceptually it must be possible: The phase offset is only defined by the
*relative* phase between RX/TX-LO.
Let's assume that both RX + TX mixer are driven by the *same* LO but the RX
side has an additional frequency doubler.
Then the phase relationship is ALWAYS constant. By construction.
But, that's not the situation we find ourselves in with the hardware
(including FPGA) in front of us.
The USRP just makes things complicated because RX and TX are driven by
different PLLs and allow their LO to be retuned separately. But ultimately both
PLLs are driven by the same reference (to which phase they lock) so there must
be a way to have a constant phase relationship.
Did you look at the reference I posted about Fractional-N vs Integer-N
synthesis? They behave very differently in this regard--the "phase reset"
feature helps, but in this case, the UBX was never designed to
maintain constant phase offsets between RX/TX (because this is a very very
unusual case), PARTICULARLY ACROSS RETUNES.
Quite apart from what the PLL synthesizers are doing, there's the
DDC/DUC within the FPGA, and they are driven by what amounts to a
digital oscillator, and THOSE digital oscillators aren't shared,
either. Sharing phase constancy across TX/RX was never a design goal
of the hardware.
Now, having said all that, it may be the case that there are specific
configurations in which this can be made to work, and I'm in discussions
with R&D about that. Details like what the management policy is for
the phase-accumulators in the DDC/DUC digital oscillators matters,
along with hardware details like whether the RX and TX synthesizers
shared a control bus or whether it's in parallel really matter, for example.
Thanks,
Luke
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