Hi Z. Cao, What version of UHD are you running on your old E310?
Generally the max sample rate supported by the ARM is ~10 MS/s. With regards to the sample rate error you saw when trying to run at 40 MS/s, try adding the device args: "master_clock_rate=40e6". >Does RFNoC included in the default image in E310 now? If so, UHD 3.14.1 branch and all its examples supports RFNoC? Which E310 image doesn’t include RFNoC? With UHD 3.15 RFNoC will be enabled by default, on 3.14.x, it must be enabled with the cmake arg -DENABLE_RFNOC=ON. Regards, Nate Temple On Thu, Oct 31, 2019 at 12:09 PM zcao--- via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > We are testing a newly acquired E310 by running UHD example > tx_samples_from_files.cpp. The data file we use was used in testing other > USRP E310 devices so we know it is correct. For this particular E310, we > ran into underrun problem. The screen output looks like the following: > > root@ettus-e3xx-sg3:~/localinstall# > usr/lib/uhd/examples/tx_samples_from_file --rate 4000000 --freq 2512000000 > --ant TX/RX --gain 30 --bw 1000000 --file ./pkt_0238_2.dat --repeat --spb > 5000 > > Creating the usrp device with: ... > [INFO] [UHD] linux; GNU C++ version 4.9.2; Boost_105700; > UHD_3.14.1.HEAD-0-gbfb9c1c7 > [INFO] [E300] Loading FPGA image: > /home/root/localinstall/usr/share/uhd/images/usrp_e310_fpga_sg3.bit... > [INFO] [E300] FPGA image loaded > [INFO] [E300] Detecting internal GPS > .... [INFO] [E300] GPSDO found > [INFO] [E300] Initializing core control (global registers)... > > [INFO] [E300] Performing register loopback test... > [INFO] [E300] Register loopback test passed > [INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD100000000000) > [INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000) > [INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0000000000002) > [WARNING] [RFNOC] [legacy_compat] No FIFO detected. Higher transmit rates > may encounter errors. > Using Device: Single USRP: > Device: E-Series Device > Mboard 0: E3XX SG3 > RX Channel: 0 > RX DSP: 0 > RX Dboard: A > RX Subdev: FE-RX2 > RX Channel: 1 > RX DSP: 1 > RX Dboard: A > RX Subdev: FE-RX1 > RX Channel: 2 > RX DSP: 0 > RX Dboard: A > RX Subdev: FE-RX2 > RX Channel: 3 > RX DSP: 1 > RX Dboard: A > RX Subdev: FE-RX1 > TX Channel: 0 > TX DSP: 0 > TX Dboard: A > TX Subdev: FE-TX2 > TX Channel: 1 > TX DSP: 1 > TX Dboard: A > TX Subdev: FE-TX1 > TX Channel: 2 > TX DSP: 0 > TX Dboard: A > TX Subdev: FE-TX2 > TX Channel: 3 > TX DSP: 1 > TX Dboard: A > TX Subdev: FE-TX1 > > Setting TX Rate: 4.000000 Msps... > Actual TX Rate: 4.000000 Msps... > > Setting TX Freq: 2512.000000 MHz... > Setting TX LO Offset: 0.000000 MHz... > Actual TX Freq: 2512.000000 MHz... > > Setting TX Gain: 30.000000 dB... > Actual TX Gain: 30.000000 dB... > > Setting TX Bandwidth: 1.000000 MHz... > Actual TX Bandwidth: 1.000000 MHz... > > Checking TX: LO: locked ... > Press Ctrl + C to stop streaming... > > UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU^C > Done! > U > UUUUUUUUUU[INFO] [E300] Loading FPGA image: > /home/root/localinstall/usr/share/uhd/images/usrp_e3xx_fpga_idle_sg3.bit... > [INFO] [E300] FPGA image loaded > > Any suggestions on where we should go from here are appreciated. We have a > few questions. > > 1. Does RFNoC included in the default image in E310 now? If so, UHD 3.14.1 > branch and all its examples supports RFNoC? Which E310 image doesn’t > include RFNoC? > > 2. On our old E310 platforms acquired 3 years ago, we can run TX rate > @40MSPS. However, for this E310, there is a warning sign above says : > [WARNING] [RFNOC] [legacy_compat] No FIFO detected. Higher transmit rates > may encounter errors. > > In fact, we tried to set rate high @40MSPS, we got the following messages: > > [WARNING] [MULTI_USRP] The hardware does not support the requested TX > sample rate: > Target sample rate: 40.000000 MSps > Actual sample rate: 16.000000 MSps > > > Are we using the right FPGA images? > > > Thanks, > Z. Cao > > > > > > > > > > > > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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