Hi Felix, Sounds like you've had a lot of progress since you wrote the first email; well done!
Keep at it and send questions as needed. We're happy to help! Best regards, EJ On Tue, Aug 13, 2019 at 3:41 AM Felix Greiwe via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > i found myself not to be familiar with the Core Concept of interpreting > Data in FPGA's as IQ-Data. After i partitioned my 32 Bit Input Data in 16 > Bit I and 16 Bit Q Data, and additionally edited my testbench similar to > the addsub testbench of one of the pre-installed rfnoc-blocks, my > testbench passed. > > In the following link I stumbled upon some help regarding the testbenches > and other useful information which helped me a lot. > > > http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2018-March/056076.html > > Best regards, > > Felix Greiwe > > > > > Hello together, > > > > recently i started RFNoC development using an USRP x310. After finishing > > the RFNoC getting started Guide i created an OOT Module including VHDL. > > First i simply forwarded the Input Data to the output which worked just > > fine. After that i wanted to add a constant, for example 5_dec., to my > > signal (32 Bit) and receive the sum as an output in the testbench. Here > > the problems started: > > Instead of receiving 5,6,7,8,9 for input of 0,1,2,3,4; i got > > > > 5+2^32+2^34 > > 6+2^32+2^34 > > 7+2^32+2^34 etc. > > > > I figured out, that i got the right results in 32 Bit, but that somewhere > > in the axi_wrapper and/or the noc_shell my results gets concatted to 64 > > Bit, always using the first result (here the number 5) as the 32 msb's > and > > the actual sum results as the lsb's thus changing my signal. > > > > Wondering, i tested some more stuff like just setting the lowest bit of > 32 > > Bit input Data Vector to one etc. and get the same problems of wrong > > vector connections. > > > > Only when i changed the width parameter of the axi_wrapper to 64 Bit (and > > also sending 64 Bit Data) i got the expected results. > > > > Now my question: Is this a bug or am i maybe using the axi_wrapper wrong? > > I could not find an error comparing my code to the one of the > > tutorial_gain block. > > > > Any help to understand this is appreciated. > > > > Sincerly > > > > Felix > > > > > > > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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