Hi,
I download the latest version of UHD and follow the instruction of
building RFNOC. However, I met the attached errors. I noticed that Peter
Horvath has the same problem.
Appreciate if anyone can help me.
Regards
Hao
========================================================
Warnings: 211
Critical Warnings: 0
Errors: 0
BUILDER: Releasing IP location:
/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/aurora_64b66b_pcs_pma
Using parser configuration from:
/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/dev_config.json
[00:00:00] Executing command: vivado -mode batch -source
/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/build_x300.tcl -log build.log
-journa l x300.jou
CRITICAL WARNING: [filemgmt 20-1440] File
'/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/use
r_design/rtl/clocking/mig_7series_v4_2_tempmon.v'
already exists in the project as a part of sub-design file
'/home/hao.chen1/rfnoc/src/uhd-fpga
/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'.
Explicitly adding the file outside the scope of the sub-design can lead to
unintended behaviors and is not recommended.
[00:00:11] Current task: Initialization +++ Current Phase: Starting
[00:00:11] Current task: Initialization +++ Current Phase: Finished
[00:00:11] Executing Tcl: synth_design -top x300 -part xc7k410tffg900-2
-verilog_define BUILD_1G=1 -verilog_define BUILD_10G=1 -verilog_define S
FP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define
RFNOC=1 -verilog_define X310=1 -verilog_define GIT_HASH=32'hfb615a5a
[00:00:11] Starting Synthesis Command
[00:02:08] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [Constraints 18-1056] Clock 'FPGA_CLK' completely overrides
clock 'FPGA_CLK_p'.
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/timing.xdc:72]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ioport2_clk]'. [/home/hao.chen1/rfnoc/src/u
hd-fpga/usrp3/top/x300/timing.xdc:72]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ioport2_clk]'. [/home/hao.chen1/rfnoc/src/u
hd-fpga/usrp3/top/x300/timing.xdc:73]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks rio40_clk]'. [/home/hao.chen1/rfnoc/src/uhd
-fpga/usrp3/top/x300/timing.xdc:73]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/timing.xdc:74]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks radio_clk]'. [/home/hao.chen1/rfnoc/src/uhd
-fpga/usrp3/top/x300/timing.xdc:74]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk_div2]'. [/home/hao.chen1/rfnoc/src/
uhd-fpga/usrp3/top/x300/timing.xdc:75]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks radio_clk]'. [/home/hao.chen1/rfnoc/src/uhd
-fpga/usrp3/top/x300/timing.xdc:75]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ioport2_clk]'. [/home/hao.chen1/rfnoc/src/u
hd-fpga/usrp3/top/x300/timing.xdc:76]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks IoPort2Wrapperx/RxLowSpeedClk]'. [/home/hao
.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/timing.xdc:76]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/timing.xdc:77]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ce_clk]'. [/home/hao.chen1/rfnoc/src/uhd-fp
ga/usrp3/top/x300/timing.xdc:78]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/timing.xdc:78]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ce_clk]'. [/home/hao.chen1/rfnoc/src/uhd-fp
ga/usrp3/top/x300/timing.xdc:79]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks radio_clk]'. [/home/hao.chen1/rfnoc/src/uhd
-fpga/usrp3/top/x300/timing.xdc:79]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/x300_10ge.xdc:13]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk_div2]'. [/home/hao.chen1/rfnoc/src/
uhd-fpga/usrp3/top/x300/x300_10ge.xdc:14]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/
ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}]'.
[/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_10ge.xdc:15]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/
ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}]'.
[/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/x300_10ge.xdc:16]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/x300_1ge.xdc:13]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/x300_1ge.xdc:14]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/x300_1ge.xdc:15]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/x300_dram.xdc:8]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks mmcm_ps_clk_bufg_in]'. [/home/hao.chen1/rfn
oc/src/uhd-fpga/usrp3/top/x300/x300_dram.xdc:8]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/x300_dram.xdc:9]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ddr3_axi_clk]'. [/home/hao.chen1/rfnoc/src/
uhd-fpga/usrp3/top/x300/x300_dram.xdc:9]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks bus_clk]'. [/home/hao.chen1/rfnoc/src/uhd-f
pga/usrp3/top/x300/x300_dram.xdc:10]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found
for '-group [get_clocks ddr3_axi_clk_x2]'. [/home/hao.chen1/rfnoc/s
rc/uhd-fpga/usrp3/top/x300/x300_dram.xdc:10]
[00:04:01] Current task: Synthesis +++ Current Phase: Handling Custom Attributes
[00:04:01] Current task: Synthesis +++ Current Phase: RTL Component Statistics
[00:04:01] Current task: Synthesis +++ Current Phase: RTL Hierarchical
Component Statistics
[00:04:02] Current task: Synthesis +++ Current Phase: Part Resource Summary
[00:05:53] Current task: Synthesis +++ Current Phase: Cross Boundary and Area
Optimization
[00:05:59] Current task: Synthesis +++ Current Phase: Applying XDC Timing
Constraints
[00:06:34] Current task: Synthesis +++ Current Phase: Timing Optimization
[00:07:07] Current task: Synthesis +++ Current Phase: Technology Mapping
[00:07:07] Current task: Synthesis +++ Current Phase: IO Insertion
[00:07:10] Current task: Synthesis +++ Current Phase: Flattening Before IO
Insertion
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_clk with 1st driver
pin 'radio_clk_gen/CLK_OUT1' [/home/hao.chen1/rfnoc/src/uhd-fpga
/usrp3/top/x300/x300.v:381]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_clk with 2nd driver
pin 'bus_clk_gen/CLK_OUT4' [/home/hao.chen1/rfnoc/src/uhd-fpga/u
srp3/top/x300/x300.v:284]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_rst with 1st driver
pin 'radio_reset_sync/reset_double_sync/synchronizer_false_path/
stages[9].value_reg[9][0]/Q'
[/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/lib/control/synchronizer_impl.v:33]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_rst with 2nd driver
pin 'ce_reset_sync/reset_double_sync/synchronizer_false_path/sta
ges[9].value_reg[9][0]/Q'
[/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/lib/control/synchronizer_impl.v:33]
[00:07:29] Current task: Synthesis +++ Current Phase: Final Netlist Cleanup
[00:07:42] Current task: Synthesis +++ Current Phase: Renaming Generated
Instances
[00:07:53] Current task: Synthesis +++ Current Phase: Rebuilding User Hierarchy
[00:07:56] Current task: Synthesis +++ Current Phase: Renaming Generated Ports
[00:07:57] Current task: Synthesis +++ Current Phase: Handling Custom Attributes
[00:07:57] Current task: Synthesis +++ Current Phase: Renaming Generated Nets
[00:07:59] Current task: Synthesis +++ Current Phase: Writing Synthesis Report
[00:07:59] Current task: Synthesis +++ Current Phase: Finished
[00:07:59] Translating Synthesized Netlist
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb31'. The
XDC file /home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/build-i
p/xc7k410tffg900-2/axi_hb31/constraints/fir_compiler_v7_2.xdc will
not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb47'. The
XDC file /home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/build-i
p/xc7k410tffg900-2/axi_hb47/constraints/fir_compiler_v7_2.xdc will
not be read for any cell of this module.
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for
'-to [get_pins int_reset_sync/reset_int*/PRE]'. [/home/hao.chen1/r
fnoc/src/uhd-fpga/usrp3/top/x300/timing.xdc:591]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for
'-to [get_pins int_div2_reset_sync/reset_int*/PRE]'. [/home/hao.ch
en1/rfnoc/src/uhd-fpga/usrp3/top/x300/timing.xdc:592]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for
'-to [get_pins ce_reset_sync/reset_int*/PRE]'. [/home/hao.chen1/rf
noc/src/uhd-fpga/usrp3/top/x300/timing.xdc:593]
CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for
'-to [get_pins radio_reset_sync/reset_int*/PRE]'. [/home/hao.chen1
/rfnoc/src/uhd-fpga/usrp3/top/x300/timing.xdc:594]
[00:11:03] Current task: Translating Synthesized Netlist +++ Current Phase:
Starting
[00:11:03] Current task: Translating Synthesized Netlist +++ Current Phase:
Finished
[00:11:03] Executing Tcl: report_drc -ruledeck methodology_checks -file
/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/me
thodology.rpt
[00:11:03] Starting DRC Command
[00:12:21] Current task: DRC +++ Current Phase: Starting
[00:12:22] Current task: DRC +++ Current Phase: Finished
[00:12:22] Executing Tcl: opt_design -directive NoBramPowerOpt
[00:12:22] Starting Logic Optimization Command
[00:12:22] Current task: Logic Optimization +++ Current Phase: Starting
[00:12:22] Current task: Logic Optimization +++ Current Phase: Finished
[00:12:22] Starting DRC Task
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4 has
multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and bus_clk_gen/
inst/clkout4_buf/O.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
multiple drivers: ce_res
et_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
and radio_reset_sync/reset_double_sync/synchronizer_false_path/st
ages[9].value_reg[9][0]/Q.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
[00:12:26] Current task: DRC +++ Current Phase: Starting
[00:12:26] Current task: DRC +++ Current Phase: Finished
[00:12:26] Process terminated. Status: Failure
========================================================
Warnings: 1282
Critical Warnings: 40
Errors: 4
Makefile.x300.inc:106: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Leaving directory '/home/hao.chen1/rfnoc/src/uhd-fpga/usrp3/top/x300'
Makefile:112: recipe for target 'X310_RFNOC_HG' failed
make: *** [X310_RFNOC_HG] Error 2
xxxx@1500003049L:~/rfnoc/src/uhd-fpga/usrp3/tools/scripts$
./uhd_image_builder.py fft -d x310 -t X310_RFNOC_HG -m 6 --fill-with-fifos
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