Hi all,
I am studying the application note "Getting Started with RFNoC Development".
I was able to complete the simulation of custom noc_block_gain, but failed in
the final stage of the synthesis.
The custom block "gain" cannot be found.
I use the following command, "./uhd_image_builder.py gain ddc fft -I
~/rfnoc/src/rfnoc-mesh/ -d n310 -t N310_RFNOC_HG -m 6 --fill-with-fifos -c".
I did specify the OOT directory during image building. I am certain I have made
all settings correct.
So far I have no clue what causes this. How to solve this problem?
PS, I use uhd 3.14.0.0, and post of imaging buiding,
****** Vivado v2018.3_AR71898 (64-bit)
**** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source run_ippack.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2018.3/data/ip'.
INFO: [Common 17-206] Exiting Vivado at Tue Jul 30 20:41:13 2019...
INFO: [HLS 200-112] Total elapsed time: 17.38 seconds; peak allocated memory:
66.934 MB.
INFO: [Common 17-206] Exiting vivado_hls at Tue Jul 30 20:41:13 2019...
BUILDER: Releasing IP location:
/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/addsub_hls
Using parser configuration from:
/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx/dev_config.json
[00:00:00] Executing command: vivado -mode batch -source
/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build_n3xx.tcl -log build.log
-journal n3xx.jou
CRITICAL WARNING: [filemgmt 20-1440] File
'/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v'
already exists in the project as a part of sub-design file
'/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/ddr3_32bit/ddr3_32bit.xci'.
Explicitly adding the file outside the scope of the sub-design can lead to
unintended behaviors and is not recommended.
[00:00:14] Current task: Initialization +++ Current Phase: Starting
[00:00:14] Current task: Initialization +++ Current Phase: Finished
[00:00:14] Executing Tcl: synth_design -top n3xx -part xc7z100ffg900-2
-verilog_define SFP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define
USE_REPLAY=1 -verilog_define BUILD_1G=1 -verilog_define BUILD_10G=1
-verilog_define RFNOC=1 -verilog_define N310=1 -verilog_define
GIT_HASH=32'hfb615a5a
[00:00:14] Starting Synthesis Command
ERROR: [Synth 8-439] module 'noc_block_gain' not found
[/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v:22]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
[/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
[/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console
or run log file for details
[00:03:48] Current task: Synthesis +++ Current Phase: Starting
[00:03:49] Current task: Synthesis +++ Current Phase: Finished
[00:03:49] Process terminated. Status: Failure
========================================================
Warnings: 407
Critical Warnings: 1
Errors: 4
Makefile.n3xx.inc:149: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Leaving directory '/home/wtt/rfnoc/src/uhd-fpga/usrp3/top/n3xx'
Makefile:133: recipe for target 'N310_RFNOC_HG' failed
make: *** [N310_RFNOC_HG] Error 2
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