Hi all,
I developed a custom correlation module in Verilog and I would like to
insert it in the usrp x310 fpga image. My goal is to send a signal
(with a usrp b205 mini) at a sampling rate of 1M and to receive it with
the usrp x310. Inside the fpga, my block will look for a certain
sequence inside the received signal.
My block is working with a 200M clock and can support data rate up to
2M.
From what I've read, it seems that the adc of the x310 is working at
200M and that this can't be changed. So my module should be placed after
the ddc chain. But this rises a few questions:
1) Where exactly in the code is the ddc chain instantiated *? Should I
do it myself ?
2) Is it possible to have a decimation rate of 200 or should it be a
power of 2 ?
3) How is the decimation rate controlled ? From what I understand it's
from the sampling rate parameter in GnuRadio. Am I right ?
Thanks !
* For some reasons, I'm working with uhd 3.10.3
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