Hello, I'm trying to bake an RFNoC image from the latest master, using Vivado 2018.3. However, I get DRC errors:
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_clk with 1st driver pin 'bus_clk_gen/CLK_OUT4' [/home/x/fpga/usrp3/top/x300/x300.v:284] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_clk with 2nd driver pin 'radio_clk_gen/CLK_OUT1' [/home/x/fpga/usrp3/top/x300/x300.v:381] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_rst with 1st driver pin 'ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q' [/home/x/fpga/usrp3/lib/control/synchronizer_impl.v:33] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin ce_rst with 2nd driver pin 'radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q' [/home/x/fpga/usrp3/lib/control/synchronizer_impl.v:33] ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4 has multiple drivers: bus_clk_gen/inst/clkout4_buf/O, and radio_clk_gen/inst/clkout1_buf/O. ERROR: [DRC MDRV-1] Multiple Driver Nets: Net radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has multiple drivers: ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q, and radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q. By looking at x300.v, it is not clear why these nets would be multiply driven. No custom modules, freshly cloned repo, with the command line: ./uhd_image_builder.py duc ddc --device X310 --target X310_RFNOC_XG Is the latest master considered to be usable? Am I missing something? Any help appreciated. Best regards, Peter
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