On Wed, Jun 5, 2019 at 4:41 PM Jason Matusiak via USRP-users <
usrp-users@lists.ettus.com> wrote:
> OK, thanks everyone. I guess I have some superhet reading up to do 🙂.
>
In a nutshell, it's _always_ using LO offset :)
The RF path always brings the signal to some IF (150 MHz IIRC), then the
DDC blocks do the shift to baseband DC digitally.
So it's pretty much like if you had set the lo_offset = 150 MHz.
The finer points are :
- It's not doing I/Q sampling, it uses one ADC for one channel and the
other for the second one.
- It's actually using band-pass sampling since the IF is higer than fs / 2.
But of course that means the hardware DDC blocks in the fpga are used
already and that's why you can't (and there would be no point anyway) to
apply some second level of lo_offset.
Cheers,
Sylvain
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