I don't know what your block does, so I don't know which to recommend. The rfnoc-modtool testbench example is fine, as are most of the existing testbenches in usrp3/lib/rfnoc.
Ignore the error you're having now, spend some time setting up a testbench. I promise it will save you time in the end. On Wed, Apr 24, 2019 at 8:06 AM Xingjian Chen <xingj...@umass.edu> wrote: > Dear Nick, > > Thank you for the quick reply. I assigned eob, has_time, payload_length, > src_sid, next_dst_sid, future_vita_time in another module. There is some > logic to define when and how to change those values. Sorry for the > confusion. > > I haven't simulated this. Could you think of a relevant testbench example > I can start with? Thank you. > > ------------------------------ > *From:* Nick Foster <bistrom...@gmail.com> > *Sent:* Wednesday, April 24, 2019 10:39:42 AM > *To:* Xingjian Chen > *Cc:* USRP-users@lists.ettus.com; usrp-users-boun...@lists.ettus.com > *Subject:* Re: [USRP-users] How to insert an EOB for rfnoc transmission? > > Also, just to be clear, I usually see "no response packet" when I've > messed up something in the CHDR. Looking more closely, you're using vita > time set to "future_vita_time", but I don't see where that's assigned, > either. Similarly for has_time and payload_length. > > Have you simulated this? It is very unwise to go straight to FPGA before > simulating in a testbench. RFNoC comes with very good testbench examples. > > On Wed, Apr 24, 2019 at 7:37 AM Nick Foster <bistrom...@gmail.com> wrote: > >> Are you assigning a value for eob? You declare it, but I don't see where >> you assign it. >> >> On Wed, Apr 24, 2019 at 7:15 AM Xingjian Chen via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> Hi Guys, >>> Good morning. I am wondering how to insert an EOB in Verilog code to the >>> radio. What I have tried is cvita_hdr_modify as below. I think just change >>> EOB bit should put the tx radio into the idle state. However, when the >>> EOB changed, my E312 returned an error as below. There is a register I >>> used for updating coefficients in FPGA, but it should not be related to >>> EOB. Thank you. >>> >>> wire [63:0] future_vita_time ; >>> wire eob; >>> wire has_time; >>> cvita_hdr_modify cvita_hdr_modify_data ( >>> .header_in(m_axis_data_tuser), >>> .header_out(s_axis_data_tuser), >>> .use_pkt_type(1'b0), .pkt_type(), >>> .use_has_time(1'b1), .has_time(has_time), >>> .use_eob(1'b1), .eob(eob), >>> .use_seqnum(1'b0), .seqnum(), >>> .use_length(1'b1), .length(payload_length), >>> .use_src_sid(1'b1), .src_sid(src_sid), >>> .use_dst_sid(1'b1), .dst_sid(next_dst_sid), >>> .use_vita_time(1'b1), .vita_time(future_vita_time)); >>> >>> Returned Error: >>> sr_write() failed: EnvironmentError: IOError: Block ctrl (CE_01_Port_20) >>> no response packet >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>
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