Hi Xingjian,

If I understood your problem correctly, you are expecting two equal
streams to arrive at the same time on the output, but you have an AXI
Crossbar in the middle. This is a packet-based router, so it is hard
to predict its behavior timing-wise, and I don't think this would be
the right approach even if you could. I recommend you should make use
of the timestamp in CHDR headers, and instruct your radio_cores to
output your samples at the same time that way.

Regards,

Leo.

On Mon, Apr 8, 2019 at 11:52 AM Xingjian Chen via USRP-users
<usrp-users@lists.ettus.com> wrote:
>
> Dear All,
> I am doing FPGA debugging with an E312. I have two exactly same signal 
> generation RFNOC modules run simultaneously. The waveform is triggered by a 
> reference clock generated in Verilog at the same time. What I found is that 
> when the waveform went from RFNOC module to noc_block_radio_core in 
> tx_control_gen3.v, the initial phase relative to the reference clock changed, 
> the waveform in one tx channel is delayed by half cycle than the other tx 
> channel. And when I tested and recorded one of the channels' timing by 
> chipscope ila tool. There is a roughly 50% chance that I get a right initial 
> phase and 50% chance that I get the half cycle delayed version.
> I think this is due to competition between two tx modules when both were 
> sending packets to the bus, the AXI Wrapper or the NOC shell randomly picked 
> one of them to go first and then alternating the data transferring.
> What I would like to do is to transmit two fixed initial phase waveforms 
> relative to a reference clock. Could you please give me some hint that how to 
> deal with this problem?
> I think maybe I can make two different RFNOC modules such that the first tx 
> module always waiting for the second module at the starting moment. Maybe I 
> should play with the "s_axis_data_tvalid". But I don't know how to set this 
> up with AXI Wrapper and NOC shell. Thank you for your help!
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-- 
Leandro Echevarría

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