Hi Andrew,

Please take note of this section of the KB with regards to FPGA
modifications: https://kb.ettus.com/X300/X310#FPGA_User_Modifications

The PCIe interface and LvFpga_Chinch_Interface cannot be modified, even if
you are not using PCIe as a transport, as it will brick the flash memory:
https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/x300/x300.v#L656

As Leandro mentioned, removing the DDC/DUCs will result in the most gains.
You could possibly adjust the HB and max CIC within the DDC/DUC to reduce
utilization at the cost of reducing your resampling range.

Regards,
Nate Temple

On Tue, Jan 29, 2019 at 11:55 AM Leandro Echevarría via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hey Andrew,
>
> Have you confirmed the available resources are not enough for your
> purpose?
> If so, I'd suggest you run the build command with the GUI option on,
> implement the design using the Vivado interface, and run a
> post-implementation utilization report to see which blocks are consuming
> the most. Still, there is not much that can be taken away without bricking
> the core, but if I recall correctly removing the DDCs and DUCs could
> release about 5 or 10% of the resources. This would, of course, reduce the
> functionality, forcing you to run the device at full rate all the time.
>
> Regards,
>
> Leo
>
> On Tue, Jan 29, 2019 at 4:15 PM Andrew Thommesen via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi,
>>
>> I was wondering if there is any way to reduce the resources used by the
>> default RFNoC image. It currently utilises ~50% of the Kintex-7 FPGA of the
>> Ettus X310, and I want to make more resources available (LUTs and FFs
>> mainly) for bespoke firmware development.
>>
>> Thanks,
>>
>> Andy
>>
>> Sent from Outlook <http://aka.ms/weboutlook>
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>> USRP-users@lists.ettus.com
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>>
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