Some more thoughts...

Are you programming the axi_rate_change SR_N, SR_M, and SR_CONFIG registers
when you run on hardware? You might be able to do this with the XML
definition, but you may also need a block controller like the
ddc_block_ctrl_impl in uhd. Don't forgot the config register-- this seems
to latch in the N & M values.

I probably wouldn't worry about the axi_tag_time unless timed commands are
really important to your application... For most "run of the mill" rfnoc
applications with gnuradio it's usually safe to ignore timed commands, so
you might be able to simplify some logic if you wanted to take out the
axi_tag_time.


As another example you can reference, see this unmerged PR from a month or
so ago that combines a DUC and DDC into a single rfnoc block:
https://github.com/EttusResearch/fpga/pull/32 Also the corresponding uhd PR
with the software controller:
https://github.com/EttusResearch/uhd/pull/219/files

(These PRs didn't make it into the main branches but they will live on,
soon, in a new consolidated OOT repo)

EJ

On Tue, Dec 18, 2018, 6:19 PM Andrew Danowitz <and...@whitefoxdefense.com
wrote:

> Thanks for the reply. I do set simple_mode and I propagate tuser into and
> out of axi_rate_change the same way noc_block_ddc does. I also have my
> block running properly in Vivado simulation. Is there anything else I
> should check? I also included axi_tag_time. Could that be causing an issue?
>
> Thanks!
> Andrew
>
> On Tue, Dec 18, 2018 at 10:11 AM EJ Kreinar <ejkrei...@gmail.com> wrote:
>
>> Hi Andrew,
>>
>> Quick thoughts:
>> - Are you setting SIMPLE_MODE(0) in the axi_wrapper?
>> - Are you propagating tuser into and out of the axi_rate_change block?
>>
>> The axi_rate_change block updates tuser, which the axi_wrapper uses to
>> create output packets when SIMPLE_MODE is disabled.
>>
>> Also, have you run in a simulation testbench? Simulation should be able
>> to expose these issues before targetting hardware to make debugging a bit
>> easier.
>>
>> EJ
>>
>>
>>
>> On Tue, Dec 18, 2018 at 1:04 PM Andrew Danowitz via USRP-users <
>> usrp-users@lists.ettus.com> wrote:
>>
>>> Hi all,
>>>
>>> I'm trying to create an rfnoc block that takes in a stream of data at
>>> Sample rate n, does some processing to turn i-q values into real samples,
>>> and outputs data at a rate of n/2 by packing real values into both i and q
>>> channels of the output stream. I've tried to incorporate the
>>> axi_rate_change block and the axi_tag_time block a-la noc_block_ddc, but
>>> whenever I try to run it I keep getting a timeout error. If I take out the
>>> channel packing block and keep the rate n-to-n, the module works fine.
>>>
>>> Does anyone have any advice?
>>>
>>> Thanks,
>>> Andrew
>>>
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