Hi Jason,
I had mentioned this same issue on Oct 29 ("RFNoC build issue for OOT
block"), but never got any response. I had to abandon RFNoC development on
the N310 in favor of doing it on the X310 and I have not returned to the
N310.
Rob
On Fri, Dec 14, 2018 at 10:20 AM Jason Matusiak via USRP-users <
usrp-users@lists.ettus.com> wrote:
> I finally got an N310 to play with. I was trying to build a custom RFNoC
> FPGA image, but it keeps erroring out.
>
> The command I am running is:
> ./uhd_image_builder.py -d N310 -t N310_RFNOC_XG -I
> /opt/gnuradio/N310/src/rfnoc-nocblocks -y
> /opt/gnuradio/N310/src/rfnoc-nocblocks/fpga_build/n310_4ddc_2keepMinN_2split.yml
>
> The debug is:
>
> ./uhd_image_builder.py -d N310 -t N310_RFNOC_XG -I
> /opt/gnuradio/N310/src/rfnoc-nocblocks -y
> /opt/gnuradio/N310/src/rfnoc-nocblocks/fpga_build/n310_4ddc_2keepMinN_2split.yml
> Using yml file. Ignoring command line blocks arguments
> ddc
> {'extraports': None, 'parameters': {'NOC_ID': "64'hDDC0_0000_0000_0000",
> 'NUM_CHAINS': 2}, 'clock': 'ce'}
> ddc
> {'extraports': None, 'parameters': {'NOC_ID': "64'hDDC0_0000_0000_0000",
> 'NUM_CHAINS': 2}, 'clock': 'ce'}
> ddc
> {'extraports': None, 'parameters': {'NOC_ID': "64'hDDC0_0000_0000_0001",
> 'NUM_CHAINS': 1}, 'clock': 'ce'}
> ddc
> {'extraports': None, 'parameters': {'NOC_ID': "64'hDDC0_0000_0000_0001",
> 'NUM_CHAINS': 1}, 'clock': 'ce'}
> keepMinN
> {'extraports': None, 'parameters': None, 'clock': 'ce'}
> keepMinN
> {'extraports': None, 'parameters': None, 'clock': 'ce'}
> split_stream
> {'extraports': None, 'parameters': None, 'clock': 'ce'}
> split_stream
> {'extraports': None, 'parameters': None, 'clock': 'ce'}
> [{'block': 'ddc', 'parameters': {'NOC_ID': "64'hDDC0_0000_0000_0000",
> 'NUM_CHAINS': 2}}, {'block': 'ddc', 'parameters': {'NOC_ID':
> "64'hDDC0_0000_0000_0000", 'NUM_CHAINS': 2}}, {'block': 'ddc',
> 'parameters': {'NOC_ID': "64'hDDC0_0000_0000_0001", 'NUM_CHAINS': 1}},
> {'block': 'ddc', 'parameters': {'NOC_ID': "64'hDDC0_0000_0000_0001",
> 'NUM_CHAINS': 1}}, {'block': 'keepMinN', 'parameters': None}, {'block':
> 'keepMinN', 'parameters': None}, {'block': 'split_stream', 'parameters':
> None}, {'block': 'split_stream', 'parameters': None}]
> --Using the following blocks to generate image:
> * ddc
> * ddc
> * ddc
> * ddc
> * keepMinN
> * keepMinN
> * split_stream
> * split_stream
> Adding CE instantiation file for 'N310_RFNOC_XG'
> changing temporarily working directory to
> /opt/gnuradio/N310/src/uhd/fpga-src/usrp3/tools/scripts/../../top/n3xx
> Setting up a 64-bit FPGA build environment for the USRP-N3x0...
> - Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
>
> Environment successfully initialized.
> make -f Makefile.n3xx.inc bin NAME=N310_RFNOC_XG ARCH=zynq
> PART_ID=xc7z100/ffg900/-2 SFP0_10GBE=1 SFP1_10GBE=1 BUILD_10G=1 RFNOC=1
> N310=1 TOP_MODULE=n3xx EXTRA_DEFS="SFP0_10GBE=1 SFP1_10GBE=1 BUILD_10G=1
> RFNOC=1 N310=1"
> make[1]: Entering directory
> `/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx'
> BUILDER: Checking tools...
> * GNU bash, version 4.2.46(2)-release (x86_64-redhat-linux-gnu)
> * Python 2.7.5
> * Vivado v2017.4 (64-bit)
> Using parser configuration from:
> /opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/dev_config.json
> [00:00:00] Executing command: vivado -mode batch -source
> /opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/build_n3xx.tcl -log
> build.log -journal n3xx.jou
> CRITICAL WARNING: [filemgmt 20-1440] File
> '/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v'
> already exists in the project as a part of sub-design file
> '/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/ddr3_32bit/ddr3_32bit.xci'.
> Explicitly adding the file outside the scope of the sub-design can lead to
> unintended behaviors and is not recommended.
> [00:00:33] Current task: Initialization +++ Current Phase: Starting
> [00:00:33] Current task: Initialization +++ Current Phase: Finished
> [00:00:33] Executing Tcl: synth_design -top n3xx -part xc7z100ffg900-2
> -verilog_define SFP0_10GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define
> BUILD_10G=1 -verilog_define RFNOC=1 -verilog_define N310=1 -verilog_define
> GIT_HASH=32'hf494ae8b
> [00:00:33] Starting Synthesis Command
> CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module
> ram_2port
> [/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/n310_ps_bd/n310_ps_bd/control/ram_2port.v:12]
> CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module
> cvita_dest_lookup
> [/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/n310_ps_bd/n310_ps_bd/packet_proc/cvita_dest_lookup.v:11]
> CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module
> cvita_chunker
> [/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/n310_ps_bd/n310_ps_bd/packet_proc/cvita_chunker.v:15]
> ERROR: [Synth 8-439] module 'noc_block_keepMinN' not found
> [/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v:54]
> ERROR: [Synth 8-285] failed synthesizing module 'n3xx_core'
> [/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
> ERROR: [Synth 8-285] failed synthesizing module 'n3xx'
> [/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
> ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
> console or run log file for details
> [00:10:47] Current task: Synthesis +++ Current Phase: Starting
> [00:10:48] Current task: Synthesis +++ Current Phase: Finished
> [00:10:48] Process terminated. Status: Failure
>
> ========================================================
> Warnings: 323
> Critical Warnings: 4
> Errors: 4
>
> make[1]: *** [bin] Error 1
> make[1]: Leaving directory
> `/opt/gnuradio/N310/src/uhd/fpga-src/usrp3/top/n3xx'
> make: *** [N310_RFNOC_XG] Error 2
>
>
>
> I cannot for the life of me figure out why it can't find my OOT module.
> This is the same command I have used for an e310 and x310 that worked fine.
>
> Any advice?
>
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>
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