Hi Wade, I see that a new rfnoc_ce_auto_inst_n310.v has been committed to github to address this issue (commit 8b37fd8). But, I don't see what good this will do given that this file is auto-generated by the uhd_image_builder.py script which will just overwrite this file. Additionally, the script will insert the following two lines rather than the ones you used. Will this work as well? wire ce_clk = radio_clk; wire ce_rst = radio_rst;
Rob On Fri, Oct 19, 2018 at 12:48 PM Wade Fife via USRP-users < usrp-users@lists.ettus.com> wrote: > Dan, > > The UHD exception you saw appears to be due to ce_clk and ce_rst not be > connected in the RFNoC variant that you built (N310_RFNOC_HG; it works in > N310_HG). You can fix this for now by connecting them in > rfnoc_ce_auto_inst_n310.v (see diff below, or refer to > rfnoc_ce_default_inst_n310.v as an example of how to set ce_clk and > ce_rst). I'll look into getting this fixed permanently. > > diff --git a/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v > b/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v > index 176dad48..e61038d7 100644 > --- a/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v > +++ b/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v > @@ -14,6 +14,9 @@ > end > endgenerate > > + wire ce_clk = bus_clk; > + wire ce_rst = bus_rst; > + > noc_block_ddc #(.NOC_ID(64'hDDC0_0000_0000_0001), .NUM_CHAINS(1)) > inst_noc_block_ddc ( > .bus_clk(bus_clk), .bus_rst(bus_rst), > .ce_clk(ce_clk), .ce_rst(ce_rst), > > Thanks, > > Wade > > > On Thu, Oct 18, 2018 at 4:06 PM Lundberg, Daniel < > daniel.lundb...@gtri.gatech.edu> wrote: > >> I tried nuking everything and doing a clean install of the master branch, >> but still get the same errors. Here’s a couple of warnings I did not copy >> in my first e-mail that occur when running the uhd_image_loader with the >> new fpga .bit: >> >> >> >> [WARNING] [MPMD IMAGE LOADER] RuntimeError: Component file does not >> exist: /path to build/n3xx.dts >> >> [WARNING] [MPM.PeriphManager] Actual minor compat ahead of expected >> compat for component ‘FPGA’. Expect 5.2 Actual: 5.3 >> >> >> >> The second one seems to indicate a minor mismatch between the UHD master >> and the FPGA .bit, correct? >> >> >> >> *From:* Wade Fife <wade.f...@ettus.com> >> *Sent:* Thursday, October 18, 2018 11:37 AM >> *To:* Lundberg, Daniel <daniel.lundb...@gtri.gatech.edu> >> *Cc:* usrp-users <USRP-users@lists.ettus.com> >> *Subject:* Re: [USRP-users] Building N310 replay example >> >> >> >> Hi Dan, >> >> >> >> I'll see if I can reproduce this with the current master. In the meantime >> I suggest just double checking that the fpga-src submodule is also up to >> date. Currently, uhd master is at 7130059 and fpga should be at 340bb07. I >> know that error would occur with older versions of the FPGA code. >> >> >> >> Thanks, >> >> >> >> Wade >> >> >> >> On Thu, Oct 18, 2018 at 9:38 AM Lundberg, Daniel via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >> I am trying to to work with the RFNoc replay block on an N310. I have >> followed the instructions here: >> https://kb.ettus.com/Using_the_RFNoC_Replay_Block >> >> >> >> I have Ubuntu 18.04, and the current master branch of UHD. >> >> >> >> Those instructions are for the X3xx, but I tried modifying them for the >> N310, by doing “make N310_RFNOC_HG” after changing to “USE_REPLAY=1” >> >> This build of the n3xx.bit completed with no errors, but with 67 >> “critical warnings. I attempted to forge on anyways, but the >> uhd_image_loader has several errors (copied at the end of this message). >> >> >> >> My question is whether or not anyone has successfully enabled the replay >> block on an N310 with the current master build? I have not intentionally >> deviated from the prescribed script in any way to get to this point, so I >> am a bit lost on how to proceed. >> >> >> >> Thank you, >> >> Dan >> >> >> >> [ERROR] [UHD] Exception caught in safe-call. >> >> in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with >> uhd::endianness_t _endianness = (uhd::endianness_t)0] >> >> at /home/epuser/workarea-uhd/uhd/host/lib/rfnoc/ctrl_iface.cpp:60 >> >> this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl >> (CE_03_Port_60) no response packet - AssertionError: bool(buff) >> >> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) >> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long >> unsigned int] >> >> at /home/epuser/workarea-uhd/uhd/host/lib/rfnoc/ctrl_iface.cpp:155 >> >> >> >> [ERROR] [MPMD] Failure during block enumeration: EnvironmentError: >> IOError: Block ctrl (CE_03_Port_60) no response packet - AssertionError: >> bool(buff) >> >> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) >> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long >> unsigned int] >> >> at /home/epuser/workarea-uhd/uhd/host/lib/rfnoc/ctrl_iface.cpp:155 >> >> >> >> terminate called after throwing an instance of 'uhd::io_error' >> >> what(): EnvironmentError: IOError: [0/Replay_0] sr_write() failed: >> EnvironmentError: IOError: Block ctrl (CE_00_Port_30) no response packet - >> AssertionError: bool(buff) >> >> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) >> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long >> unsigned int] >> >> at /home/epuser/workarea-uhd/uhd/host/lib/rfnoc/ctrl_iface.cpp:155 >> >> >> >> >> >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
_______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
