Hey folks, I designed a custom block that writes and reads data to the external DDR3 RAM. I'm using NoC Shell + 64-bit-wide CHDR framers and deframers, all of them within the bus_clk (there clock domain crossing to the 300 MHz DDR clock happens closer to the AXI DMA block). The writing portion seems to be working OK, but I'm having trouble in certain situations when reading and streaming back to the host.
My test was creating an rx streamer in my host computer, and triggering reads to the DRAM to the host. This seems to work OK for small bursts, but when requesting longer streams with several full-size packets (almost 8000 bytes) it reaches a moment where str_src_ready (the ready from the NoC Shell to my CHDR framer) is de-asserted, and it never goes up again. What could be happening? I understand the sustained speed from reading from the external RAM can be a little higher than the 10 Gbps of my link to the host computer, but shouldn't the back-pressure regulate this bottleneck? As for the RX streamer, I still do not understand what spp and spb I should use if my packets are of variable length (specially, if I trigger a stream of a given length, the packets will contain 1996 samples up until the last one, that is usually smaller). Thanks in advance! Leo
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