Hi Arnika, Good catch. It looks like the commit here changed HLS generation: https://github.com/EttusResearch/fpga/commit/615d9b8eeb94ee2d19c3b1e7aa526d4999495e05
I tested the addsub_hls testbench, which runs fine. However, it seems as though the devices (e300, n3xx, x310) have no process to include the addsub output sources in the build. I havent had a chance to confirm success yet, but here's a possible fix pushed to my fork: https://github.com/ejk43/fpga/tree/fix-new-hls-builds EJ On Mon, Sep 10, 2018 at 10:19 AM Arnika Zoe via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi all, > After updating fpga source to most recent master branch, I noticed that > rfnoc blocks, which uses HLS generated IP cores, are no longer synthesizing > with the project. Furthermore, viv_hls_ip_builder is not starting at all. I > think that the reason of this problem is missing HLS targets in main x300 > makefile (Makefile.x300.inc). Could someone confirm this issue / propose > solution? > > Error from building example provided by Ettus (addsub_hls): > > ERROR: [Synth 8-439] module 'addsub_hls' not found > [/workarea/fpga/usrp3/lib/rfnoc/noc_block_addsub.v:88] > ERROR: [Synth 8-285] failed synthesizing module 'noc_block_addsub' > [/workarea/fpga/usrp3/lib/rfnoc/noc_block_addsub.v:8] > ERROR: [Synth 8-285] failed synthesizing module 'x300_core' > [/workarea/fpga/usrp3/top/x300/x300_core.v:8] > ERROR: [Synth 8-285] failed synthesizing module 'x300' > [/workarea/fpga/usrp3/top/x300/x300.v:20] > ERROR: [Common 17-69] Command failed: Synthesis failed - please see the > console or run log file for details > [00:03:07] Current task: Synthesis +++ Current Phase: Starting > [00:03:07] Current task: Synthesis +++ Current Phase: Finished > [00:03:07] Process terminated. Status: Failure > -- > Best regards > Arnika > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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