There is no conceptual reason why you can’t build an RFNoC design on B210, it uses the same USRP3 base architecture and FPGA source files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all the implementation work for RFNoC is done using Xilinx’s Vivado design tools which support only the newer FPGA architectures like Zynq (Artix) and Kintex…Spartan6 users are stuck with ISE14 forever, so in practical terms, no, it’s not possible without you completely recreating all that infrastructure.
-Ian > On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users > <usrp-users@lists.ettus.com> wrote: > > Hi All, > Is it possible to generate RFNoC blocks for the B210? I can't find a lot of > information about it. Can some one show me the URL if there is a website > talking about it? > > Cheers > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
