Hello, I have installed RFNoC and UHD driver. But I cant load a RFNoC image in my USRP-X310:
cruiz@DASPC034:~$ sudo uhd_images_downloader [INFO] Images destination: /usr/local/share/uhd/images [INFO] No inventory file found at /usr/local/share/uhd/images/inventory.json. Creating an empty one. 00006 kB / 00006 kB (100%) usrp1_b100_fw_default-g6bea23d.zip 15845 kB / 15845 kB (100%) n3xx_n310_fpga_default-ge0f552c.zip 02757 kB / 02757 kB (100%) usrp2_n210_fpga_default-g6bea23d.zip 02032 kB / 02032 kB (100%) n230_n230_fpga_default-g4bb66b3.zip 00522 kB / 00522 kB (100%) usrp1_b100_fpga_default-g6bea23d.zip 00465 kB / 00465 kB (100%) b2xx_b200_fpga_default-g1c568e6.zip 02415 kB / 02415 kB (100%) usrp2_n200_fpga_default-g6bea23d.zip 28428 kB / 28428 kB (100%) x3xx_x310_fpga_default-g4bb66b3.zip 00517 kB / 00517 kB (100%) b2xx_b205mini_fpga_default-g1c568e6.zip 27146 kB / 27146 kB (100%) x3xx_x300_fpga_default-g4bb66b3.zip 00017 kB / 00017 kB (100%) octoclock_octoclock_fw_default-g14000041.zip 04839 kB / 04839 kB (100%) usb_common_windrv_default-g14000041.zip 00007 kB / 00007 kB (100%) usrp2_usrp2_fw_default-g6bea23d.zip 00009 kB / 00009 kB (100%) usrp2_n200_fw_default-g6bea23d.zip 00450 kB / 00450 kB (100%) usrp2_usrp2_fpga_default-g6bea23d.zip 00144 kB / 00144 kB (100%) b2xx_common_fw_default-g14000041.zip 00473 kB / 00473 kB (100%) b2xx_b200mini_fpga_default-g1c568e6.zip 00319 kB / 00319 kB (100%) usrp1_usrp1_fpga_default-g6bea23d.zip 00009 kB / 00009 kB (100%) usrp2_n210_fw_default-g6bea23d.zip 11489 kB / 11489 kB (100%) n3xx_n300_fpga_default-ge0f552c.zip 04422 kB / 04422 kB (100%) e3xx_e310_fpga_default-g1c568e6.zip 00859 kB / 00859 kB (100%) b2xx_b210_fpga_default-g1c568e6.zip [INFO] Images download complete. cruiz@DASPO048:~$ uhd_usrp_probe [INFO] [UHD] linux; GNU C++ version 7.3.0; Boost_106501; UHD_4.0.0.rfnoc-devel-788-g1f8463cc [INFO] [X300] X300 initialization sequence... [INFO] [X300] Maximum frame size: 1472 bytes. [INFO] [X300] Radio 1x clock: 200 MHz [INFO] [GPS] No GPSDO found [INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D00000000000) [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1323 MB/s) [INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1303 MB/s) [INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD100000000001) [WARNING] [0/Radio_0] [0/Radio_0] defines 2 input buffer sizes, but 1 input ports [INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD100000000001) [WARNING] [0/Radio_1] [0/Radio_1] defines 2 input buffer sizes, but 1 input ports [INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000) [INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0000000000000) [INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0000000000000) [INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0000000000000) [WARNING] [X300] Cannot update master clock rate! X300 Series does not allow changing the clock rate during runtime. _____________________________________________________ / | Device: X-Series Device | _____________________________________________________ | / | | Mboard: X310 | | revision: 11 | | revision_compat: 7 | | product: 30818 | | mac-addr0: 00:80:2f:18:e8:21 | | mac-addr1: 00:80:2f:18:e8:22 | | gateway: 192.168.10.1 | | ip-addr0: 192.168.10.2 | | subnet0: 255.255.255.0 | | ip-addr1: 192.168.20.2 | | subnet1: 255.255.255.0 | | ip-addr2: 192.168.30.2 | | subnet2: 255.255.255.0 | | ip-addr3: 192.168.40.2 | | subnet3: 255.255.255.0 | | serial: 314BF05 | | FW Version: 6.0 | | FPGA Version: 35.0 | | FPGA git hash: 000000f | | RFNoC capable: Yes | | | | Time sources: internal, external, gpsdo | | Clock sources: internal, external, gpsdo | | Sensors: ref_locked | | _____________________________________________________ | | / | | | RX Dboard: A | | | ID: TwinRX Rev C (0x0095) | | | Serial: 3137E4D | | | _____________________________________________________ | | | / | | | | RX Frontend: 0 | | | | Name: TwinRX RX0 | | | | Antennas: RX1, RX2 | | | | Sensors: lo_locked | | | | Freq range: 10.000 to 6000.000 MHz | | | | Gain range all: 0.0 to 93.0 step 1.0 dB | | | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz | | | | Connection Type: II | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | RX Frontend: 1 | | | | Name: TwinRX RX1 | | | | Antennas: RX1, RX2 | | | | Sensors: lo_locked | | | | Freq range: 10.000 to 6000.000 MHz | | | | Gain range all: 0.0 to 93.0 step 1.0 dB | | | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz | | | | Connection Type: QQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | RX Codec: A | | | | Name: ads62p48 | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB | | _____________________________________________________ | | / | | | RX Dboard: B | | | _____________________________________________________ | | | / | | | | RX Frontend: 0 | | | | Name: Unknown (0xffff) - 0 | | | | Antennas: | | | | Sensors: | | | | Freq range: 0.000 to 0.000 MHz | | | | Gain Elements: None | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | RX Codec: B | | | | Name: ads62p48 | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB | | _____________________________________________________ | | / | | | TX Dboard: A | | | ID: Unknown (0x0094) | | | Serial: 3135BD2 | | | _____________________________________________________ | | | / | | | | TX Frontend: 0 | | | | Name: Unknown (0x0094) - 0 | | | | Antennas: | | | | Sensors: | | | | Freq range: 0.000 to 0.000 MHz | | | | Gain Elements: None | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | TX Codec: A | | | | Name: ad9146 | | | | Gain Elements: None | | _____________________________________________________ | | / | | | TX Dboard: B | | | _____________________________________________________ | | | / | | | | TX Frontend: 0 | | | | Name: Unknown (0xffff) - 0 | | | | Antennas: | | | | Sensors: | | | | Freq range: 0.000 to 0.000 MHz | | | | Gain Elements: None | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | TX Codec: B | | | | Name: ad9146 | | | | Gain Elements: None | | _____________________________________________________ | | / | | | RFNoC blocks on this device: | | | | | | * DmaFIFO_0 | | | * Radio_0 | | | * Radio_1 | | | * DDC_0 | | | * DDC_1 | | | * DUC_0 | | | * DUC_1 Where are the RFNoC images? :/ cruiz@DASPC034:~$ ls /usr/local/share/uhd/images/ -1 bit inventory.json octoclock_bootloader.hex octoclock_r4_fw.hex usrp1_fpga_4rx.rbf usrp1_fpga.rbf usrp1_fw.ihx usrp2_fpga.bin usrp2_fw.bin usrp_b100_fpga_2rx.bin usrp_b100_fpga.bin usrp_b100_fw.ihx usrp_b200_fpga.bin usrp_b200_fw.hex usrp_b200mini_fpga.bin usrp_b205mini_fpga.bin usrp_b210_fpga.bin usrp_e310_fpga.bin usrp_e310_fpga.bit usrp_e310_fpga.rpt usrp_e310_fpga_sg3.bin usrp_e310_fpga_sg3.bit usrp_e310_fpga_sg3.rpt usrp_e3xx_fpga_idle.bin usrp_e3xx_fpga_idle.bit usrp_e3xx_fpga_idle.rpt usrp_e3xx_fpga_idle_sg3.bin usrp_e3xx_fpga_idle_sg3.bit usrp_e3xx_fpga_idle_sg3.rpt usrp_n200_fw.bin usrp_n200_r2_fpga.bin usrp_n200_r3_fpga.bin usrp_n200_r4_fpga.bin usrp_n210_fw.bin usrp_n210_r2_fpga.bin usrp_n210_r3_fpga.bin usrp_n210_r4_fpga.bin usrp_n230_fpga.bin usrp_n230_fpga.bit usrp_n230_fpga.rpt usrp_n300_fpga_HG.bit usrp_n300_fpga_HG.bit.md5 usrp_n300_fpga_HG.dts usrp_n300_fpga_HG.dts.md5 usrp_n300_fpga_HG.rpt usrp_n300_fpga_WX.bit usrp_n300_fpga_WX.bit.md5 usrp_n300_fpga_WX.dts usrp_n300_fpga_WX.dts.md5 usrp_n300_fpga_WX.rpt usrp_n300_fpga_XG.bit usrp_n300_fpga_XG.bit.md5 usrp_n300_fpga_XG.dts usrp_n300_fpga_XG.dts.md5 usrp_n300_fpga_XG.rpt usrp_n310_fpga_HG.bit usrp_n310_fpga_HG.bit.md5 usrp_n310_fpga_HG.dts usrp_n310_fpga_HG.dts.md5 usrp_n310_fpga_HG.rpt usrp_n310_fpga_WX.bit usrp_n310_fpga_WX.bit.md5 usrp_n310_fpga_WX.dts usrp_n310_fpga_WX.dts.md5 usrp_n310_fpga_WX.rpt usrp_n310_fpga_XG.bit usrp_n310_fpga_XG.bit.md5 usrp_n310_fpga_XG.dts usrp_n310_fpga_XG.dts.md5 usrp_n310_fpga_XG.rpt usrp_x300_fpga_HG.bin usrp_x300_fpga_HG.bit usrp_x300_fpga_HG.lvbitx usrp_x300_fpga_HG.rpt usrp_x300_fpga_XG.bin usrp_x300_fpga_XG.bit usrp_x300_fpga_XG.lvbitx usrp_x300_fpga_XG.rpt usrp_x310_fpga_HG.bin usrp_x310_fpga_HG.bit usrp_x310_fpga_HG.lvbitx usrp_x310_fpga_HG.rpt usrp_x310_fpga_XG.bin usrp_x310_fpga_XG.bit usrp_x310_fpga_XG.lvbitx usrp_x310_fpga_XG.rpt winusb_driver Thank you.
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