Hi All, I'm seeing some odd behavior after upgrading uhd-fpga to Vivado 2017.4. It appears some of my larger testbenches take a noticeably longer time to complete the "update_compile_order" command before progressing.
Here's an example (see elapsed time of 10+ minutes, after the update_compile_order tcl command with the -verbose option): ``` # set_property top $sim_top [get_filesets $sim_fileset] # set_property default_lib xil_defaultlib [current_project] # update_compile_order -fileset sim_1 -verbose update_compile_order: *Time (s): cpu = 00:09:30 ; elapsed = 00:10:24 *. Memory (MB): peak = 1218.863 ; gain = 20.000 ; free physical = 21745 ; free virtual = 28625 # set_property target_simulator $simulator [current_project] # if [expr [string equal $simulator "XSim"] == 1] { # set_property verilog_define "WORKING_DIR=\"$working_dir\"" [get_filesets $sim_fileset] # } else { # set_property verilog_define "WORKING_DIR=$working_dir" [get_filesets $sim_fileset] # } [...etc...] ``` The same OOT module testbench running Vivado 2015.4 and uhd-fpga commit 434943b takes 18 seconds: ``` # set_property top $sim_top [get_filesets $sim_fileset] # set_property default_lib xil_defaultlib [current_project] # update_compile_order -fileset sim_1 -verbose update_compile_order: *Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 *. Memory (MB): peak = 979.520 ; gain = 42.805 ; free physical = 12432 ; free virtual = 26832 # set_property target_simulator $simulator [current_project] # if [expr [string equal $simulator "XSim"] == 1] { # set_property verilog_define "WORKING_DIR=\"$working_dir\"" [get_filesets $sim_fileset] # } else { # set_property verilog_define "WORKING_DIR=$working_dir" [get_filesets $sim_fileset] # } [...etc...] ``` I havent tested or debugged exhaustively yet, but it will definitely become a point of friction for simulations to take 10+ minutes to load. Has anyone else seen this behavior? Is it a regression in Vivado? Thoughts appreciated. Thanks! EJ
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