Thanks Neel, We have tested a plain 10 GbE ‘loopback’ – i.e. send packet out, have external hardware turn it around and receive it. The latency is about 10 us with very tight variance. So, the UDP stack (yes I know we were talking about PCIe before) is not the limiting factor. PCIe should be even lower latency since the network card goes through the PCIe interface anyway.
We are looking into the latency introduced by the FPGA. I see a major change since UHD 9 (rfnoc) that makes it harder to trace where all the FIFOs are. Also, I see the SRAM FIFO option is no longer available. (not that it would make much difference, just a few clock cycles). I am also trying to understand the flow control on the UHD TX. Does the UHD interface wait for a packet from the FPGA before sending out the first packet to the FPGA? If so, is the period of the ‘status’ packets from the FPGA limiting out latency? One approach I am thinking of is: do not use the UHD for TX at all. Build up my own CHRD packets and send them out. What do you think? Unfortunately we cannot use RFNoC (at least in no obvious way) because we need to combine inputs from many USRPs at the same time. In the worst case, I am considering dropping UHD entirely and using the X310s as ‘raw iron.’ I.e. change the FPGA code to just send ADC / DAC samples to/from PCIe. That way I can control all the buffers myself. No looking forward to that at all … _______________________ Eugene Grayver, Ph.D. Aerospace Corp., Sr. Eng. Spec. Tel: 310.336.1274 ________________________ From: Neel Pandeya [mailto:neel.pand...@ettus.com] Sent: Saturday, May 19, 2018 10:05 AM To: Eugene Grayver <eugene.gray...@aero.org> Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] Minimize latency over PCIe on X310 Hello Eugene: I would not suggest modifying the PCIe transfer block sizes. Although the PCIe bus might be able to achieve latencies of 10 us, there is additional latency introduced by UHD and the FPGA. In order to achieve a latency less than 10us, you would have to do processing in the FPGA, using the RFNoC framework. You won't be able to achieve such a low latency passing samples between the host computer and the radio. --Neel Pandeya On 25 April 2018 at 17:20, Eugene Grayver via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: One more comment on the latency issue. I increased the sample rate to 100 Msps and setup the machine to stay in full-frequency (i.e. no p-states) mode. The minimum latency I can achieve is now 110 us. I instrumented rtdsc timer to check the delay between receiving a packet and sending it out. The delay between the two is very steady between 9-15 us. So, the latency is about 10 packet’s worth. Can one of the developers chime in? _______________________ Eugene Grayver, Ph.D. Aerospace Corp., Sr. Eng. Spec. Tel: 310.336.1274 ________________________ _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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