Hello Eugene: I would not suggest modifying the PCIe transfer block sizes. Although the PCIe bus might be able to achieve latencies of 10 us, there is additional latency introduced by UHD and the FPGA. In order to achieve a latency less than 10us, you would have to do processing in the FPGA, using the RFNoC framework. You won't be able to achieve such a low latency passing samples between the host computer and the radio.
--Neel Pandeya On 25 April 2018 at 17:20, Eugene Grayver via USRP-users < usrp-users@lists.ettus.com> wrote: > One more comment on the latency issue. I increased the sample rate to 100 > Msps and setup the machine to stay in full-frequency (i.e. no p-states) > mode. The minimum latency I can achieve is now 110 us. > > > > I instrumented rtdsc timer to check the delay between receiving a packet > and sending it out. The delay between the two is very steady between 9-15 > us. So, the latency is about 10 packet’s worth. > > > > Can one of the developers chime in? > > > > _______________________ > Eugene Grayver, Ph.D. > Aerospace Corp., Sr. Eng. Spec. > Tel: 310.336.1274 > ________________________ > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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