Hello Peter, thank you for noticing this. We will take care of this shortly.
- Nicolas On Tue, May 8, 2018 at 10:57 AM, Peter Horvath via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > > the clocking scheme has been recently changed, as of > https://github.com/EttusResearch/fpga/commit/ > 89957c3f30d3e17ddd43622277cbec299b207805 > > But it seems that the rfnocmodtool Verilog template did not receive the > required changes, i.e., it leaves bus_clk and reset unconnected on the > axi_wrapper instance. This will cripple any AXI stuff, and the test bench > will run indefinitely waiting for AXI transactions in vain. Is it possible? > (https://github.com/EttusResearch/gr-ettus/blob/ > master/python/rfnoc_modtool/templates.py line 608ff) > Thanks, > Peter > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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