Hi all,
I am trying to add the schmidlcox, fft and and eq to my X310.
Looks like the S&C block does not meet timing constraints. This is the
report from Vivado.
Any help would be much appreciated, thank you...
Francesco
---------------------------------------------------------------------------------------------------
From Clock: ce_clk
To Clock: ce_clk
Setup : 2475 Failing Endpoints, Worst Slack -1.315ns, Total
Violation -244.308ns
Hold : 0 Failing Endpoints, Worst Slack 0.020ns, Total
Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 1.565ns, Total
Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -1.315ns (required time - arrival time)
Source:
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_neg_data_y_swap/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/i_no_async_controls.output_reg[37]/C
(rising edge-triggered cell FDRE clocked by
ce_clk {rise@0.000ns fall@2.333ns period=4.667ns})
Destination:
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/i_no_async_controls.output_reg[36]/D
(rising edge-triggered cell FDRE clocked by
ce_clk {rise@0.000ns fall@2.333ns period=4.667ns})
Path Group: ce_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.667ns (ce_clk rise@4.667ns - ce_clk
rise@0.000ns)
Data Path Delay: 5.921ns (logic 2.833ns (47.850%) route
3.088ns (52.150%))
Logic Levels: 11 (CARRY4=10 LUT1=1)
Clock Path Skew: -0.056ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -1.669ns = ( 2.998 - 4.667 )
Source Clock Delay (SCD): -1.925ns
Clock Pessimism Removal (CPR): -0.312ns
Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.082ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns)
Netlist Resource(s)
-------------------------------------------------------------------
-------------------
(clock ce_clk rise edge) 0.000 0.000 r
AB27 0.000 0.000 r
FPGA_125MHz_CLK (IN)
net (fo=0) 0.000 0.000
FPGA_125MHz_CLK
AB27 IBUF (Prop_ibuf_I_O) 1.504 1.504 r
fpga_125MHz_clk_buf/O
net (fo=2, routed) 1.098 2.602
bus_clk_gen/inst/CLK_IN1
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
-8.213 -5.611 r
bus_clk_gen/inst/plle2_adv_inst/CLKOUT3
net (fo=1, routed) 2.213 -3.398
bus_clk_gen/inst/CLK_OUT4_bus_clk_gen
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.093 -3.305 r
bus_clk_gen/inst/clkout4_buf/O
net (fo=53802, routed) 1.380 -1.925
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_neg_data_y_swap/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/CLK
SLICE_X121Y257 FDRE r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_neg_data_y_swap/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/i_no_async_controls.output_reg[37]/C
-------------------------------------------------------------------
-------------------
SLICE_X121Y257 FDRE (Prop_fdre_C_Q) 0.204 -1.721 f
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_neg_data_y_swap/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/i_no_async_controls.output_reg[37]/Q
net (fo=117, routed) 0.116 -1.605
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_neg_data_y_swap/i_no_async_controls.output_reg[1][36]
SLICE_X121Y257 LUT1 (Prop_lut1_I0_O) 0.126 -1.479 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_neg_data_y_swap/inst_i_1/O
net (fo=14, routed) 0.238 -1.241
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/lopt_31
SLICE_X121Y258 CARRY4 (Prop_carry4_S[0]_CO[3])
0.302 -0.939 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.carrymux0_CARRY4/CO[3]
net (fo=2, routed) 0.606 -0.333
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_3
SLICE_X121Y264 CARRY4 (Prop_carry4_CYINIT_CO[3])
0.287 -0.046 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_CARRY4/CO[3]
net (fo=2, routed) 0.333 0.287
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_7
SLICE_X119Y264 CARRY4 (Prop_carry4_CYINIT_CO[3])
0.287 0.574 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux_CARRY4/CO[3]
net (fo=2, routed) 0.420 0.994
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_11
SLICE_X119Y263 CARRY4 (Prop_carry4_CYINIT_CO[3])
0.287 1.281 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux_CARRY4/CO[3]
net (fo=2, routed) 0.420 1.701
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_15
SLICE_X114Y263 CARRY4 (Prop_carry4_CYINIT_CO[3])
0.297 1.998 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux_CARRY4/CO[3]
net (fo=2, routed) 0.339 2.337
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_19
SLICE_X114Y265 CARRY4 (Prop_carry4_CYINIT_CO[3])
0.297 2.634 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux_CARRY4/CO[3]
net (fo=1, routed) 0.000 2.634
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_23
SLICE_X114Y266 CARRY4 (Prop_carry4_CI_CO[3])
0.054 2.688 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[24].carrymux_CARRY4/CO[3]
net (fo=1, routed) 0.000 2.688
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_27
SLICE_X114Y267 CARRY4 (Prop_carry4_CI_CO[3])
0.054 2.742 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[28].carrymux_CARRY4/CO[3]
net (fo=2, routed) 0.339 3.081
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_31
SLICE_X114Y269 CARRY4 (Prop_carry4_CYINIT_CO[2])
0.302 3.383 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[32].carrymux_CARRY4/CO[2]
net (fo=1, routed) 0.277 3.660
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple_34
SLICE_X113Y269 CARRY4 (Prop_carry4_CYINIT_O[0])
0.336 3.996 r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carrychaingen[35].carryxor_CARRY4/O[0]
net (fo=1, routed) 0.000 3.996
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/D[35]
SLICE_X113Y269 FDRE r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/i_no_async_controls.output_reg[36]/D
-------------------------------------------------------------------
-------------------
(clock ce_clk rise edge) 4.667 4.667 r
AB27 0.000 4.667 r
FPGA_125MHz_CLK (IN)
net (fo=0) 0.000 4.667
FPGA_125MHz_CLK
AB27 IBUF (Prop_ibuf_I_O) 1.372 6.039 r
fpga_125MHz_clk_buf/O
net (fo=2, routed) 1.001 7.040
bus_clk_gen/inst/CLK_IN1
PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
-7.410 -0.370 r
bus_clk_gen/inst/plle2_adv_inst/CLKOUT3
net (fo=1, routed) 2.084 1.714
bus_clk_gen/inst/CLK_OUT4_bus_clk_gen
BUFGCTRL_X0Y11 BUFG (Prop_bufg_I_O) 0.083 1.797 r
bus_clk_gen/inst/clkout4_buf/O
net (fo=53802, routed) 1.201 2.998
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/CLK
SLICE_X113Y269 FDRE r
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/i_no_async_controls.output_reg[36]/C
clock pessimism -0.312 2.686
clock uncertainty -0.054 2.632
SLICE_X113Y269 FDRE (Setup_fdre_C_D) 0.049 2.681
x300_core/inst_schmidl_cox/schmidl_cox/complex_to_magphase_int32/U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/phase_slice/phase_plus_atan/inst/i_baseblox.i_baseblox_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/i_no_async_controls.output_reg[36]
-------------------------------------------------------------------
required time 2.681
arrival time -3.996
-------------------------------------------------------------------
slack -1.315
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