Hey everybody, I've begun working on an X310 board, and I need to make modifications to the Verilog code to include my own code. My strength is on HDL design, but I lack experience on the software part. I've got some questions (in order from most urgent to more annecdotical) I'd very much appreciate you'd help me with:
* I see the rfnoc-devel branch on the Github repository hasn't been updated in the last 6 months, and grepping code I've seen you've included "RFNoC stuff" in the maint branch, which is the one I'm currently using. The thing is I don't see the Python scripts to create RFNoC OOT modules anymore. I've got no worries as to how to integrate my modules inside the Verilog (I saw those scripts were somehow about automating instantiation code), but I'm a little lost as to WHAT part of the UHD API should I modify and recompile in order for a custom RFNoC module to be recognized by the host computer and be able to communicate with it. The guides and application notes about this also seem to be a little outdated. Any hint? * Is the AXI Crossbar configured in any way from the host? Or is there just a mapping between the crossbar ports / modules ID and the blocks the host understands should be inside the FPGA? Where is the "signal path" (i.e.: DBA-RX2 -> DDC0 --> FFT --> host) defined? Understand I've been studying the design "upwards", reading first a lot of Verilog code, and I'm beginning to explore the API itself. * Following the last question: is it possible to address directly a certain Crossbar port from the API and send / receive samples from that RFNoC block to the host and back without changing anything within the UHD? (even if the block is not properly "recognized") Thank you so much for your help, Leo.
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