Hi all,
I have an x310 with a twinRx and would like to process coherent, time aligned data within the FPGA. However, the data is not currently time aligned and there is an offset of ~400 samples between the two channels. The RFNoC radio block is configured to receive data on both channels, with the LO of channel 1 set to companion. The output of the radio block then passes through the RFNoC DDC block that decimates from 100MSPS to 50MSPS. The decimated data then passes to a custom RFNoC block that strips out the timestamps (for loopback). It is within this custom block that the the offset is detected at the output of the AXI wrapper before any processing has taken place. Any ideas? Andy Sent from Outlook<http://aka.ms/weboutlook>
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