On 02/26/2018 09:16 AM, Piotr Krysik via USRP-users wrote:
W dniu 26.02.2018 o 12:43, Piotr Krysik via USRP-users pisze:
W dniu 26.02.2018 o 11:29, Piotr Krysik via USRP-users pisze:
W dniu 25.02.2018 o 20:08, Marcus D. Leech via USRP-users pisze:
OK, so (and apologies if this was in your previous data) what is the
average magnitude of the time discrepancy?
Usually it was about few hundreds us (random). I will try to perform
more measurements.
I measured some values of the delay - they are in the attachment.
Usually the offset is larger than what I said. It's about ~10ms.
What is interesting is that the values I got in these measurements were
always positive.
Hi Marcus,
I've finally found out what the reason for the large offset is !!
One of USRPs B210 changes master clock rate AFTER setting the internal
time counter.
I've found it out when I printed USRPs time at the end of time setting
function and seen this:
...
-- Asking for clock rate 32.000000 MHz...
-- Actually got clock rate 32.000000 MHz.
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
set_min_output_buffer on block 2 to 10000000
USRP1 time: 1.003918125
USRP2 time: 1.004056625
-- Asking for clock rate 16.000000 MHz... Asking for clock rate
16.000000 MHz...
-- Actually got clock rate 16.000000 MHz.
-- Performing timer loopback test...
-- Actually got clock rate 16.000000 MHz.
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
-- pass
...
Whole part below "USRP2 time: 1.004056625" shouldn't be there. The
device at that moment is changing its master clock rate from 32MHz to
16MHz. So what I did was setting master clock rate explicitly to 16MHz.
*This solved the issue*.
Many thanks for your advices that stimulated me to think about solution
the problem.
I'm attaching the recorder to the post, so others will be able to start
synchronizing their B210s from something that works.
Best Regards,
Piotr Krysik
Hmmm, but if you're using the same sample rate on both devices (you are,
as I recall), things should still "work out", I think?
The advice on B2xx has always been to do the clock-sync "dance" *after*
sample-rates have been set, or to force a specific master-clock
rate early on, since, indeed, the sample-rate logic can change the
master-clock rate after start-up.
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
