I would like to instantiate a Xilinx cpri core and associated logic in place of one of the ethernet blocks in the FPGA. I have experience doing this with Xilinx boards but have a few questions with the X310.
1. Has anyone tried this with the X3x0 SDR's? 2. There is a TI PLL chip that will require different programming using SPI. Does anyone have an example initialization for the clock rates required for CPRI? Thanks, Gary Parrett Integre
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