Hello, I'm working on an RFNOC design for the E310 and we will likely be very tightly constrained for space on the FPGA and are looking for ways to pre-emptively free up more resources. We believe that the ZYNQ fifo module is overprovisioned for our purposes and reducing its size could save us a significant (relative to the ZYNQ 7020) number of resources and help ensure we meet timing when the FPGA gets really full. Our current strategy for reducing the size of the ZYNQ FIFO module is to reduce the number of streaming channels supported by the H2S and S2H arbiters via a Verilog parameter. Current, this is current set to support 16 streams. Since we will likely only have two RFNOC Computation Engines we suspect that we don't need 16 streams, but, we are unsure of the total number of streams we do need. So our questions:
1. What is the minimum number of streams needed to support a single-ported RFNOC CE (we're using the NOC shell and axi wrapper to interface with the RFNOC)? In addition to the streams that we allocate I'm assuming there are at least one to support register reads and write to the NOC shell. Is this correct? 2. Can the UHD software handle a change in the number of streams supported by the ZYNQ FIFO? That is, will changing the hardware break the software in a way that we might not expect? If so, would it be possible for us to make minor alterations to the UHD software to support the change in number of streaming channels. 3. Is there any other "low-hanging fruit" that we could remove from the base RFNOC design to save space without breaking the software? Thanks in advance for the help, Josh
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