There’s a bit of history there. PHY_CLK was indeed originally connected to the FPGA. It wasn’t needed and so the S1 switch was added to that pin instead. That switch was never used and so the original signal name persists in the Verilog even though it connects to nothing.
-Ian > On Nov 5, 2017, at 5:44 AM, Michał Wróbel via USRP-users > <usrp-users@lists.ettus.com> wrote: > > Hi Robin, > > Thank you for the information. > > I experimented a bit and it turned out that the V15 pin is indeed connected > to SW1, so the schematic was more informative here. The USRP2 FPGA source > code has the pin declared, but it is not used at all > <https://github.com/EttusResearch/fpga/blob/6996ed662e5ae170e60ab8cb6de54c362cecf8d2/usrp2/top/USRP2/u2_rev3.v#L59>. > > Best regards, > Michał > > 2017-11-04 17:53 GMT+01:00 Robin Coxe <robin.c...@ettus.com > <mailto:robin.c...@ettus.com>>: > Hi Michal. The USRP2 is a discontinued product that was introduced before > Ettus Research was integrated into the National Instruments manufacturing > infrastructure. Unfortunately, the only schematics and FPGA pin > constraints files that we have on hand are the ones that you have already > located. All of the people who were involved in developing the USRP2 no > longer work at Ettus Research. > > The Xilinx XC3S2000 FPGA used on the USRP2 is the FG456 package. Detailed > information about the pinout can be found starting at p. 175 of the Xilinx > datasheet: > https://www.xilinx.com/support/documentation/data_sheets/ds099.pdf > <https://www.xilinx.com/support/documentation/data_sheets/ds099.pdf> > > You could try powering on the board and probing pin V15 with an oscilloscope > to see if you observe either a clock signal or a pulse when you press SW1. > If I had to guess, the FPGA constraints file is most likely more up to date > than the schematic. > > If you would prefer to develop on a USRP that is still a released and > actively supported, you might consider the USRP N200 or N210. > > -Robin > > > > On Sat, Nov 4, 2017 at 5:37 AM, Michał Wróbel via USRP-users > <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>> wrote: > Dear usrp-users, > > Maybe you've got the answer to my question below. > > Thanks, > Michał > > ---------- Forwarded message ---------- > From: Michał Wróbel <michal.a.wro...@gmail.com > <mailto:michal.a.wro...@gmail.com>> > Date: 2017-10-28 19:32 GMT+02:00 > Subject: USRP2 schematic vs. FPGA source discrepancy > To: supp...@ettus.com <mailto:supp...@ettus.com> > > > Dear Ettus Research support team, > > I am considering customizing USRP2 FPGA contents, however there seems to be a > discrepancy between USRP2 schematics > <https://files.ettus.com/schematics/usrp2/usrp2.pdf> and FPGA constraints > file > <https://github.com/EttusResearch/fpga/blob/maint/usrp2/top/USRP2/u2_rev3.ucf>. > On the schematics the pin V15 is connected to S1 switch, while the > constraints file attaches this pin to PHY_CLK signal. Is it possible that the > schematics and the constraints file are for different revisions of USRP2 > hardware? > > Judging from the filename I presume the FPGA constraints file is for > "revision 3". Which hardware revision do the schematics describe? Where can I > find schematics and FPGA constraints file for "USRP2 Rev 4.0", which I own? > > Thank you in advance, > Michał Wróbel > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > <http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com> > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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