Hi, I am trying to figure out how to add additional Verilog code in a separate .v file and have it build. For a simple proof-of-concept test, I started with the "tutorial" module and the "gain" block, as per the instructions in the "Getting Started" document. I then substituted this code in the noc_block_gain.v file:
Instead of: wire [31:0] i_mult_gain = i * gain; wire [31:0] q_mult_gain = q * gain; I put this: wire [31:0] i_mult_gain; wire [31:0] q_mult_gain; multTest mult1 ( .i(i), .q(q), .gain(gain), .iout(i_mult_gain), .qout(q_mult_gain) ); And then at the end of the noc_block_gain.v file, I added this: module multTest(i, q, gain, iout, qout); input [15:0] i; input [15:0] q; input [15:0] gain; output [31:0] iout; output [31:0] qout; assign iout = i * gain; assign qout = q * gain; endmodule This builds fine. However, I would like to put the multTest module code in a separate .v file. I tried just putting it in a file called multTest.v in the same directory as the noc_block_gain.v file, but I get an error that the module "multTest" can't be found. As I mentioned, this is just a simple test and my real goal is to put a significant amount of code into the additional Verilog file, and to eventually use an additional VHDL file. Any ideas? I'm guessing that there may be some additional steps. Thanks, Jim
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