Hi EJ, I just did the change and it worked! You were right, I did not notice the mistake in the indices. Thanks for pointing it out!!
Best, Luis Von: EJ Kreinar <ejkrei...@gmail.com> Datum: Mittwoch, 27. September 2017 um 15:10 An: "Torres Figueroa, Luis Angel" <luis.torres.figue...@rwth-aachen.de> Cc: "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com> Betreff: Re: [USRP-users] Building USRP Image with Vivado GUI Hi Luis, In my experience this is a very common FPGA error! It gets me very often. It's not specific to the GUI workflow... You must make sure the following factors agree in the rfnoc_ce_auto_inst.v: 1. The number of CEs localparam (NUM_CE) must equal to the actual number of CEs instantiated. (Your NUM_CE = 6, while there's only 4 CEs instantiated, included those in the generate loop) 2. The ce_i_tdata and ce_o_tdata indices need to start at 0 and progress to NUM_CE - 1. (You skip indices 0 and 1) Basically, you'll get that run time error if the software tries to interact with a CE that is not actually on the AXI crossbar. I've attached a modified version of your file that should work (though untested). Hope this helps, EJ On Wed, Sep 27, 2017 at 4:24 AM, Torres Figueroa, Luis Angel via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi folks, I want to modify and build FPGA images using the Vivado GUI, however I’m still having problems with this. Here the procedure I have followed. I have first set up the environment using the command “make X310_RFNOC_HG GUI=1” and then run the synthesis/implementation; this worked fine and I could build a correct image and load it onto the USRP. Then I modified just the rfnoc_ce_auto_inst_x310.v file (modification attached) in Vivado project mode and tried to build a new image with fewer CEs, as referred in http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-September/021709.html. However even though the building process did not show any error, after loading it onto the USRP I got the following error message: [INFO] [UHDlinux; GNU C++ version 4.8.4; Boost_105400; UHD_4.0.0.rfnoc-devel-369-g1908672f] [INFO] [X300] X300 initialization sequence... [INFO] [X300] Determining maximum frame size... [INFO] [X300] Maximum frame size: 1472 bytes. [INFO] [X300] Setup basic communication... [INFO] [X300] Loading values from EEPROM... [INFO] [X300] Setup RF frontend clocking... [INFO] [X300] Radio 1x clock:200 [INFO] [X300] Detecting internal GPSDO.... [INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.929a [ERROR] [UHD] Exception caught in safe-call. in virtual ctrl_iface_impl::~ctrl_iface_impl() at /home/ltorresf/source/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 this->peek32(0); -> EnvironmentError: IOError: Block ctrl (CE_00_Port_30) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl::wait_for_ack(bool) at /home/ltorresf/source/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 Error: EnvironmentError: IOError: Block ctrl (CE_00_Port_30) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl::wait_for_ack(bool) at /home/ltorresf/source/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 Has anyone had a similar problem and know how to solve it? Best, Luis _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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