Hello,
I have been working on getting Siggen working under E310. I built RFNOC
image with siggen for E310. I have been able to use that image to generate
a signal from RFNOC_SIGGEN -> HOST, but when I try to rung RFNOC_SIGGEN ->
RFNOC_DUC -> RFNOC_RADIO I received an error. The error I received goes
away if I start with siggen enable = FALSE.
See below, the script was modified to enable siggen after 2 seconds, and
again it does not complain, but I get absolutely no output.
Following are script and original error that I receive.
Please advise,
John
#!/usr/bin/env python2
# -*- coding: utf-8 -*-
##################################################
# GNU Radio Python Flow Graph
# Title: Rfnoc Sin Radio E310
# Generated: Thu Sep 21 14:12:08 2017
##################################################
from gnuradio import eng_notation
from gnuradio import gr
from gnuradio import uhd
from gnuradio.eng_option import eng_option
from gnuradio.filter import firdes
from optparse import OptionParser
import ettus
class RFNoc_Sin_Radio_e310(gr.top_block):
def __init__(self):
gr.top_block.__init__(self, "Rfnoc Sin Radio E310")
##################################################
# Variables
##################################################
self.samp_rate = samp_rate = 2e6
self.device3 = variable_uhd_device3_0 =
ettus.device3(uhd.device_addr_t( ",".join(('type=e3x0',
"fpga=/home/root/rfnoc/usr/share
/uhd/images/usrp_e310_fpga_RFNOC_sg3.bit")) ))
self.up_rate = up_rate = 12e6
self.gain = gain = 0.5
self.freq = freq = samp_rate/10
self.enable = enable = False
self.ampl_q = ampl_q = 1
self.ampl_i = ampl_i = 1
##################################################
# Blocks
##################################################
self.uhd_rfnoc_streamer_siggen_0 = ettus.rfnoc_generic(
self.device3,
uhd.stream_args( # TX Stream Args
cpu_format="fc32", # TODO: This must be made an option
otw_format="sc16",
args="",
),
uhd.stream_args( # RX Stream Args
cpu_format="fc32", # TODO: This must be made an option
otw_format="sc16",
args="",
),
"SigGen", -1, -1,
)
self.uhd_rfnoc_streamer_siggen_0.set_arg("spp", 364)
self.uhd_rfnoc_streamer_siggen_0.set_arg("frequency",
((2*freq)/samp_rate))
self.uhd_rfnoc_streamer_siggen_0.set_arg("waveform", "SINE_WAVE")
self.uhd_rfnoc_streamer_siggen_0.set_arg("gain", gain)
self.uhd_rfnoc_streamer_siggen_0.set_arg("enable", enable)
self.uhd_rfnoc_streamer_siggen_0.set_arg("amplitude_i",
complex(ampl_i , ampl_q).real)
self.uhd_rfnoc_streamer_siggen_0.set_arg("amplitude_q",
complex(ampl_i , ampl_q).imag)
self.uhd_rfnoc_streamer_radio_0 = ettus.rfnoc_radio(
self.device3,
uhd.stream_args( # Tx Stream Args
cpu_format="fc32",
otw_format="sc16",
args='',
),
uhd.stream_args( # Rx Stream Args
cpu_format="fc32",
otw_format="sc16",
args="", # empty
),
0, -1
)
self.uhd_rfnoc_streamer_radio_0.set_rate(up_rate)
for i in xrange(1):
self.uhd_rfnoc_streamer_radio_0.set_tx_freq(1.0e9, i)
self.uhd_rfnoc_streamer_radio_0.set_tx_gain(20, i)
self.uhd_rfnoc_streamer_radio_0.set_tx_dc_offset(True, i)
self.uhd_rfnoc_streamer_radio_0.set_tx_antenna("TX/RX", 0)
self.uhd_rfnoc_streamer_fifo_0 = ettus.rfnoc_generic(
self.device3,
uhd.stream_args( # TX Stream Args
cpu_format="fc32",
otw_format="sc16",
args="gr_vlen={0},{1}".format(1, "" if 1 == 1 else
"spp={0}".format(1)),
),
uhd.stream_args( # RX Stream Args
cpu_format="fc32",
otw_format="sc16",
args="gr_vlen={0},{1}".format(1, "" if 1 == 1 else
"spp={0}".format(1)),
),
"FIFO", -1, -1,
)
self.uhd_rfnoc_streamer_duc_0 = ettus.rfnoc_generic(
self.device3,
uhd.stream_args( # TX Stream Args
cpu_format="fc32", # TODO: This must be made an option
otw_format="sc16",
args="input_rate={},output_rate={},fullscale={},freq={}".format(samp_rate,
up_rate, 1.0, 0.0),
),
uhd.stream_args( # RX Stream Args
cpu_format="fc32", # TODO: This must be made an option
otw_format="sc16",
args="",
),
"DUC", -1, -1,
)
##################################################
# Connections
##################################################
self.device3.connect(self.uhd_rfnoc_streamer_duc_0.get_block_id(),
0, self.uhd_rfnoc_streamer_fifo_0.get_block_id(), 0)
self.device3.connect(self.uhd_rfnoc_streamer_fifo_0.get_block_id(),
0, self.uhd_rfnoc_streamer_radio_0.get_block_id(), 0)
self.device3.connect(self.uhd_rfnoc_streamer_siggen_0.get_block_id(),
0, self.uhd_rfnoc_streamer_duc_0.get_block_id(), 0)
def get_samp_rate(self):
return self.samp_rate
def set_samp_rate(self, samp_rate):
self.samp_rate = samp_rate
self.set_freq(self.samp_rate/10)
self.uhd_rfnoc_streamer_siggen_0.set_arg("frequency",
((2*self.freq)/self.samp_rate))
self.uhd_rfnoc_streamer_duc_0.set_arg("input_rate",
float(self.samp_rate))
def get_variable_uhd_device3_0(self):
return self.variable_uhd_device3_0
def set_variable_uhd_device3_0(self, variable_uhd_device3_0):
self.variable_uhd_device3_0 = variable_uhd_device3_0
def get_up_rate(self):
return self.up_rate
def set_up_rate(self, up_rate):
self.up_rate = up_rate
self.uhd_rfnoc_streamer_radio_0.set_rate(self.up_rate)
self.uhd_rfnoc_streamer_duc_0.set_arg("output_rate",
float(self.up_rate))
def get_gain(self):
return self.gain
def set_gain(self, gain):
self.gain = gain
self.uhd_rfnoc_streamer_siggen_0.set_arg("gain", self.gain)
def get_freq(self):
return self.freq
def set_freq(self, freq):
self.freq = freq
self.uhd_rfnoc_streamer_siggen_0.set_arg("frequency",
((2*self.freq)/self.samp_rate))
def get_enable(self):
return self.enable
def set_enable(self, enable):
self.enable = enable
self.uhd_rfnoc_streamer_siggen_0.set_arg("enable", self.enable)
def get_ampl_q(self):
return self.ampl_q
def set_ampl_q(self, ampl_q):
self.ampl_q = ampl_q
self.uhd_rfnoc_streamer_siggen_0.set_arg("amplitude_i",
complex(self.ampl_i , self.ampl_q).real)
self.uhd_rfnoc_streamer_siggen_0.set_arg("amplitude_q",
complex(self.ampl_i , self.ampl_q).imag)
def get_ampl_i(self):
return self.ampl_i
def set_ampl_i(self, ampl_i):
self.ampl_i = ampl_i
self.uhd_rfnoc_streamer_siggen_0.set_arg("amplitude_i",
complex(self.ampl_i , self.ampl_q).real)
self.uhd_rfnoc_streamer_siggen_0.set_arg("amplitude_q",
complex(self.ampl_i , self.ampl_q).imag)
def main(top_block_cls=RFNoc_Sin_Radio_e310, options=None):
tb = top_block_cls()
tb.start()
try:
raw_input('Press Enter to quit: ')
except EOFError:
pass
tb.stop()
tb.wait()
if __name__ == '__main__':
main()
ERROR IF START UP WITH SIGGEN ENABLED
[INFO] [UHDlinux; GNU C++ version 4.9.2; Boost_105700;
UHD_4.0.0.rfnoc-devel-369-g1908672f]
[INFO] [E300] Loading FPGA image: /home/root/rfnoc/usr/share/
uhd/images/usrp_e310_fpga_RFNOC_sg3.bit...
[INFO] [E300] FPGA image loaded
[INFO] [E300] Initializing core control (global registers)...
[INFO] [E300] Performing register loopback test...
[INFO] [E300] Register loopback test passed
[INFO] [RFNOC RADIO] Register loopback test passed
[INFO] [RFNOC RADIO] Register loopback test passed
[INFO] [AD936X] Performing CODEC loopback test...
[INFO] [AD936X] CODEC loopback test passed
[INFO] [AD936X] Performing CODEC loopback test...
[INFO] [AD936X] CODEC loopback test passed
[INFO] [CORES] Performing timer loopback test...
[INFO] [CORES] Timer loopback test passed
DEBUG: output item size: 8
DEBUG: output item size: 8
[INFO] [CORES] Performing timer loopback test...
[ERROR] [RFNOC] [CE_00_Port_10] Block ctrl bad VITA packet: ValueError: Bad
CHDR or packet fragment
[INFO] [RFNOC] 00000174
[INFO] [RFNOC] 02200000
[INFO] [RFNOC] 70D1C4E8
[INFO] [RFNOC] 7E02127D
Traceback (most recent call last):
File "./test_rfnoc_radio_tx.py", line 189, in <module>
main()
File "./test_rfnoc_radio_tx.py", line 176, in main
tb = top_block_cls()
File "./test_rfnoc_radio_tx.py", line 76, in __init__
self.uhd_rfnoc_streamer_radio_0.set_rate(up_rate)
File "/home/root/rfnoc/usr/lib/python2.7/site-packages/ettus/ettus_swig.py",
line 2548, in set_rate
return _ettus_swig.rfnoc_radio_sptr_set_rate(self, *args, **kwargs)
RuntimeError: EnvironmentError: IOError: 0/Radio_0 user_reg_read64()
failed: EnvironmentError: IOError: [0/Radio_0] sr_read64() failed:
EnvironmentError: IOError: Block ctrl (CE_00_Port_10) packet parse error -
EnvironmentError: IOError: Expected SID: 02:10>00:00 Received SID:
00:00>00:00
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