Hi all, I have been looking through some previous posts on the mailing list, for example [USRP-users] subdev spec for two channels with USRP X310 ( http://http//lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2014-July/010010.html) which suggests that it should not be possible to receive 4 channels (with the standard FPGA image and UHD) on an X300/X310, due to them only having 2 DDC blocks.
However I then saw this project ( https://github.com/EttusResearch/gr-doa) (gr-doa), which seems to suggest that, using the standard FPGA image, one can run 4 channels using 2 TwinRx daughter boards. Would that not still require 4 DDC blocks, or can a DDC block be configured to process 2 real streams? Kind regards, Joshua Sendall Joshua Sendall Radar Signal Analyst Defense, Peace, Safety and Security (DPSS) Council for Scientific and Industrial Research (CSIR) Building 44 - Room C 433 CSIR, Meiring Naude Road, Pretoria Tel: 012 841 3575 -- This message is subject to the CSIR's copyright terms and conditions, e-mail legal notice, and implemented Open Document Format (ODF) standard. The full disclaimer details can be found at http://www.csir.co.za/disclaimer.html. Please consider the environment before printing this email.
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