Hi Karan, what USRP model are we talking about?
Best regards, Marcus On 20.07.2017 07:51, Karan Suri via USRP-users wrote: > Hello USRP Users > I was able to develop an *FPGA based loop back which directs the raw > ADC data to the DAC* . The TX transmits whatever it sees on the > receive signal path. > The loop back works as expected for sampling rates upto 30 MSps but it > fails to loopback received signals at a *higher sampling rate (>40)*. > It gives the potential "uuuuuuuuu..." problem or the *underflow* > issue. I suspect this issue because of the 1G Ethernet cable which > limits the maximum data rate. > But since*I am really not sending any data into the host* I should > essentially be able to use any sampling rates upto the maximum ADC > sampling limits, irrespective of the FPGA to the host data rates. > Is there any way I can achieve a different sampling rates for the > ADC-DAC versus the FPGA-Host? Like making the ADC /DAC sampling rate > be *independent* of the Host FPGA link speed? I have to achieve a *100 > MSps sampling speed with a 1 G Ethernet card* > Any suggestions will be highly appreciated. > Thanks in anticipation > Karan Suri > University of Michigan > Research Scholar > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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