Sure: OOT_DIR = /home/jmat/rfnoc-multiaperture/rfnoc include $(OOT_DIR)/Makefile.inc
OOT_DIR = /home/jmat/rfnoc-nocblocks/rfnoc include $(OOT_DIR)/Makefile.inc You'll also need your out-of-tree makefile to agree with the OOT_DIR format. See here for example (which I think you probably have correct by now, but just in case): https://github.com/ejk43/rfnoc-ootexample Good news is that this OOT_DIR infrastructure is now in the uhd-fpga/rfnoc-devel branch as of last week. It should also be supported with uhd_image_builder.py, if you supply multiple directories as -I parameters. Let me know if this works for you. EJ On Fri, Jul 7, 2017 at 3:02 PM, Jason Matusiak < ja...@gardettoengineering.com> wrote: > Circling back to this EJ, what should I make my Makefile.OOT.inc look like > to include two directories, something like this?: > OOT_DIR = /home/jmat/rfnoc-multiaperture/rfnoc > OOT_DIR = /home/jmat/rfnoc-nocblocks/rfnoc > include $(OOT_DIR)/Makefile.inc > > > > On 06/14/2017 08:43 PM, EJ Kreinar wrote: > > Yes, this is an admitted hack, I should say. > > The assignment to MY_OOT_DIR := OOT_DIR in the > rfnoc-ootexample/rfnoc/Makefile.inc forces the evaluation of OOT_DIR > immediately, and the OOT modules uses MY_OOT_DIR from then on, for example. > I've tested this successfully with multiple different OOT repos. > > If you have a suggested improvement that's less hacky though, I'm > definitely interested :) > > EJ > > On Wed, Jun 14, 2017 at 2:08 PM, Jason Matusiak < > ja...@gardettoengineering.com> wrote: > >> EJ, >> I am creating a new RFNoC repo and thought I would go through your write >> up and see if I can find anything that we missed while you and I were >> working offline. The first thing I wondered was, in the Makefile.OOT.inc, >> can I have more than one OOT_DIR? I have one in there right now for my >> current blocks, but I am not sure how to point to a different folder >> without screwing your setup up. >> >> ~Jason >> >> >> On 05/23/2017 10:04 PM, EJ Kreinar wrote: >> >> Hi Jason and others, >> >> As a follow up, I put together an rfnoc OOT repo that uses Makefiles to >> build Vivado IP and HLS IP: https://github.com/ejk43/rfnoc-ootexample >> >> The simulations should run successfully when uhd-fpga is set up correctly >> (see readme), and also should build the OOT noc_blocks into an FPGA image >> using "make E310_RFNOC" etc etc. >> >> Hope this helps, >> EJ >> >> On Fri, May 19, 2017 at 12:08 PM, EJ Kreinar <ejkrei...@gmail.com> wrote: >> >>> Jason, >>> >>> Sure, I'd say just clone my fpga repo and apply the patch for now. >>> Quick instructions: >>> >>> 1. In your uhd-fpga repo: `git remote add ejk >>> https://github.com/ejk43/fpga.git` <https://github.com/ejk43/fpga.git> >>> a. This now sets up a remote named "ejk" which points to my fork >>> 2. Then: `git fetch ejk new_oot_includes` >>> 3. Then you can either checkout this branch (if you have no other >>> changes on your uhd-fpga repo), or cherry-pick the commits from the >>> new_oot_includes branch. >>> >>> >>> In lieu of an example OOT repo, here's how I set up my "rfnoc" folder >>> structure in the OOT repo: >>> >>> rfnoc: >>> + Makefile.inc >>> + blocks >>> + testbenches >>> + fpga-src >>> + Makefile.inc >>> >>> + noc_block_testblock.v >>> >>> + ip >>> + Makefile.inc >>> + my_ip >>> + my_ip.xci >>> + Makefile.inc >>> >>> >>> >>> Here's an example top-level Makefile.inc: >>> >>> RFNOC_MYTEST_DIR := $(OOT_DIR) >>> include $(abspath $(RFNOC_MYTEST_DIR)/fpga-src/Makefile.inc) >>> include $(abspath $(RFNOC_MYTEST_DIR)/ip/Makefile.inc) >>> >>> >>> >>> Then the fpga-src Makefile.inc: >>> >>> RFNOC_OOT_SRCS += $(addprefix $(RFNOC_MYTEST_DIR)/fpga-src/, \ >>> noc_block_testblock.v \ >>> ) >>> >>> >>> >>> Then the IP Makefile.inc (modeled after the Makefile.inc in the >>> uhd-fpga/usrp3/lib/ip: >>> >>> include $(RFNOC_MYTEST_DIR)/ip/my_ip/Makefile.inc >>> >>> LIB_MYTEST_IP_XCI_SRCS = \ >>> $(LIB_IP_MY_IP_SRCS) >>> >>> LIB_MYTEST_IP_SYNTH_OUTPUTS = \ >>> $(LIB_IP_MY_IP_OUTS) >>> >>> LIB_IP_XCI_SRCS += $(LIB_MYTEST_IP_XCI_SRCS) >>> >>> >>> >>> And finally, the Makefile.inc inside the my_ip directory (modeled after >>> the lib/ip/xxx Makefile.inc): >>> >>> include $(TOOLS_DIR)/make/viv_ip_builder.mak >>> >>> LIB_IP_MY_IP_SRCS = $(IP_BUILD_DIR)/my_ip/my_ip.xci >>> >>> LIB_IP_MY_IP_OUTS = $(addprefix $(IP_BUILD_DIR)/my_ip/, \ >>> my_ip.xci.out \ >>> synth/my_ip.vhd \ >>> ) >>> >>> $(LIB_IP_MY_IP_SRCS) $(LIB_IP_MY_IP_OUTS) : $(LIB_IP_DIR)/my_ip/my_ip >>> .xci >>> $(call BUILD_VIVADO_IP,my_ip,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_ >>> BUILD_DIR),0) >>> >>> >>> >>> It's also possible to rejigger the testbench makefiles to build the OOT >>> IP for your testbench. >>> >>> Again, I should pull this into an example OOT repo sometime soon, which >>> would make it a bit easier to have an example. Let me know if you hit any >>> problems. >>> >>> EJ >>> >>> On Fri, May 19, 2017 at 8:38 AM, Jason Matusiak < >>> ja...@gardettoengineering.com> wrote: >>> >>>> EJ, that looks exactly like what I need to do. Is there a way for me >>>> to patch in your changes so I can try to use them while we wait for Ettus >>>> to (dis)approve your PR? >>>> >>>> Thanks! >>>> ~Jason >>>> >>>> >>>> >>>> On 05/18/2017 04:11 PM, EJ Kreinar wrote: >>>> >>>> Hi Jason, >>>> >>>> I currently have a PR in to the fpga repo ( >>>> https://github.com/EttusResearch/fpga/pull/12) that adds support for >>>> linking Makefile.inc files in OOT repos. Your OOT Makefile can then build >>>> the Xilinx IP and append it to your build as needed. I've been using this >>>> approach for some time now with success for both Xilinx IP and HLS designs. >>>> >>>> I have an action to provide a sample "dummy" OOT repo with the correct >>>> Makefiles-- but I havent gotten to it yet, unfortunately-- Was waiting for >>>> confirmation if this approach will be supported in-tree in the future. I >>>> could put something together soon though if this would help. >>>> >>>> I'd also be interested in other good solutions, if anyone has an >>>> alternate approach :) >>>> >>>> EJ >>>> >>>> On Thu, May 18, 2017 at 2:22 PM, Jason Matusiak via USRP-users < >>>> usrp-users@lists.ettus.com> wrote: >>>> >>>>> I wanted to create an RFNoC block that utilized some Xilinx cores. >>>>> Where do I need to put these cores in the rfnoc-modtool project created >>>>> directory structure, and how do I go about tying that into the Vivado GUI >>>>> so I can build them up (just use the GUI=1 CL argument and do the save-as >>>>> project approach?)? >>>>> >>>>> _______________________________________________ >>>>> USRP-users mailing list >>>>> USRP-users@lists.ettus.com >>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>> >>>> >>>> >>>> >>> >> >> > >
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