There's no direct path between the FPGA and the PS-side Ethernet controller which would support this mode of operation. You have to go through the host at some point.
--n On Fri, Jul 7, 2017 at 10:16 AM Cho, Daniel J (332C) via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello – > > > > For the USRP E310/E312 I was wondering if it is possible to bypass the 10 > Msps bottleneck between FPGA and ARM processor when receiving and/or > transmitting data. Does all data streaming in and out of the USRP have to > go through the ARM processor or can we have the data bypass the ARM > processor and go straight from FPGA to Host PC via Ethernet (for > rx_samples_to_file program and tx_samples_from_file program)? > > > > Thanks > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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