Community Opportunities included in this email.
https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=3fc1352192&e=99ff097940
Email not displaying correctly? View in your browser
(https://mailchi.mp/ieee-ceda/fyi-from-ieee-ceda-378353?e=99ff097940)
CONTENTS:
* Call for Nominations: IEEE TCAD Donald O. Pederson Best Paper Award (#dop)
* Call for Papers: ASAP 2019 (#asap)
* Call for Papers: NOCS 2019 (#nocs)
* Call for Papers: IEEE JxCDC (#jxcdc)
* Call for Papers: Design&Test Special Issue (#dt)
* Call for Papers: ISLPED 2019 (#islped)
* Call for Participation: DATE 2019 (#date)
* Call for CEDA Distinguished Lecturers (#dlp)
Subscribe to our Mailing List
(https://ieee-ceda.us7.list-manage.com/subscribe?u=a56289c418698825973a992ba&id=24229fc404)
https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=23b9771e39&e=99ff097940
Follow us on Twitter
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=7de922c5ba&e=99ff097940)
https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=80427eca67&e=99ff097940
IEEE CEDA Website
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=93ac0d2bde&e=99ff097940)
https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=44f62e33e8&e=99ff097940
Facebook Page
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=2dae4c69a4&e=99ff097940)
** CALL FOR NOMINATIONS:
------------------------------------------------------------
** IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper
Award
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=a3e22ed28f&e=99ff097940)
------------------------------------------------------------
The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper
Award is sponsored by the IEEE Council on EDA and recognizes the best paper
published in the Transactions on Computer-Aided Design of Integrated Circuits
and Systems publication.
The award is based on the overall quality, the originality, the level of
contribution, the subject matter, and the timeliness of the research. Anyone
who is an author of a paper published in the Transactions on Computer-Aided
Design of Integrated Circuits and Systems during the two calendar years
preceding the award is eligible for nomination. (Papers published from 1
January 2017 to 31 December 2018 are eligible for the 2019 award.)
Self-nominations are not permitted.
Nominations should be submitted using our online form
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=bd536114c6&e=99ff097940)
by 5:00 p.m. (EST) 28 February 2019.
Before you access the online form you must have the following information and
support to complete the nomination:
* Name and email of nominator
* Title of the paper, author list, and the issue in which the paper appeared
* Reason for nomination (where applicable, explain your qualifications to
comment on the paper) -- less than 200 words
* A pdf copy of the paper to upload with nomination form
Back to Contents (#Contents)
** CALL FOR CONTRIBUTIONS:
------------------------------------------------------------
** ISLPED 2019
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=9815ebb9d6&e=99ff097940)
------------------------------------------------------------
**
------------------------------------------------------------
EPFL, Lausanne, Switzerland
29-31 July 2019
The ISLPED conference is a forum for presentation of innovative research in all
aspects of low power electronics and design, ranging from process technologies
and analog/digital circuits, simulation and synthesis tools, system-level
design and optimization, to system software and applications. The conference
features regular papers and posters, three keynote presentations, and an
industry reception. It also comprises a Design Contest with live demos which
encourages submissions from both academia and industry.
Important Deadlines:
Paper abstracts: 25 February 2019
Full paper: 4 March 2019
Design contest submissions: 3 May 2019
More information can be found here
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=2746788384&e=99ff097940)
.
Read Complete Call
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=d0d4f5f1ff&e=99ff097940)
Back to Contents (#Contents)
** CALL FOR PARTICIPATION:
------------------------------------------------------------
** DATE 2019
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=e6a2597fd0&e=99ff097940)
------------------------------------------------------------
**
------------------------------------------------------------
Firenze Fiera, Florence, Italy
25-29 March 2019
The DATE conference will take place at Firenze Fiera in Florence, Italy, from
25 to 29 March 2019 and will be chaired by Professor Jürgen Teich,
Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE. For the 22nd
successive year, DATE has prepared an exciting technical programme, which is
available online
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=5bdf150eba&e=99ff097940)
.
The registration to the conference is only possible via the online registration
platform
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=c172d6fc19&e=99ff097940)
. Please kindly note that everyone who wants to attend the conference, the
exhibition, or single sessions must register. The online registration for DATE
2019 is possible until Wednesday, 13 March 2019 12:00:00 CET. Afterwards, the
registration to the conference is only possible on-site at the registration
desk and will result in an additional on-site charge of EUR 50.00.
On behalf of the whole DATE Executive Committee, we thank you very much in
advance for your participation and are looking forward to welcoming you to DATE
2019 in Florence!
More information can be found here
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=729f8601f4&e=99ff097940)
.
Preliminary Programme Available
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=6915801113&e=99ff097940)
Back to Contents (#Contents)
** CALL FOR CEDA DISTINGUISHED LECTURERS:
------------------------------------------------------------
** 2019-2020 Term of Duty
------------------------------------------------------------
**
------------------------------------------------------------
DEADLINE
8 March 2019
The IEEE Council on Electronic Design Automation (CEDA) invites nominations for
CEDA Distinguished Lecturers (DLs). The DL Program is an outreach program of
CEDA that brings distinguished speakers from academia and industry to give
presentations to CEDA chapters, events, and industries in a variety of venues
and formats. The DLs are selected and announced in April after approval by the
CEDA EC.
Nominees must meet the following criteria:
* The DL nominee must be nominated by a CEDA member who does not have conflict
with the selection process. No self-nomination is allowed.
* If you are looking for a nominator we encourage you to contact the chair of
your corresponding CEDA Local Chapter.
* The DL nominee must be a well-recognized expert in his/her field because of
his/her research, teaching, service activities and an inspiring speaker.
Duties:
The Distinguished Lecturers will start their two-year term in April. Each
Lecturer should submit up to three lecture topics in his/her field of expertise
that will be posted on the CEDA Website. The Distinguished Lectures should be
readily available to travel within his/her geographical area upon contact by
the Chapters or appropriate organizations. Reasonable travel expenses will be
paid by the Distinguished Lecturers Program, and it is encouraged the sharing
of travel expenses with other Organizational Units (Societies, Councils, etc.)
of IEEE for joint activities. In addition, the maximum expenses limit allowed
for each for a DLP lecture include 1500 USD for intra-continental talks and a
total of 2500 USD for inter-continental talks. Moreover, IEEE CEDA can only
cover Economy Fare flights.
Please return completed nomination form
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=35b1d4fbd1&e=99ff097940)
to the CEDA DLP Manager, Tsung-Yi Ho
(mailto:dl.prog...@ieee-ceda.com?subject=CEDA%20DL%20Program) .
More information can be found here
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=00481b33a4&e=99ff097940)
.
Back to Contents (#Contents)
** CALL FOR PAPERS:
------------------------------------------------------------
** ASAP 2019
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=1ff33010a4&e=99ff097940)
------------------------------------------------------------
**
------------------------------------------------------------
Cornell Tech, New York, USA
15-17 July 2019
The history of the event traces back to the International Workshop on Systolic
Arrays, organized in 1986 in Oxford, UK. It later developed into the
International Conference on Application Specific Array Processors. With its
current title, it was organized for the first time in Chicago, USA in 1996.
Since then it has alternated between Europe and North-America. The conference
will cover the theory and practice of application-specific systems,
architectures, and processors. The 2019 conference will build upon traditional
strengths in areas such as computer arithmetic, cryptography, compression,
signal and image processing, network processing, reconfigurable computing,
application-specific instruction-set processors, and hardware accelerators.
Important Deadlines:
Abstract deadline: 2 April 2019
Submission deadline: 8 April 2019
Decision notification: 6 May 2019
Camera ready version: 29 May 2019
More information can be found here
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=6df677bbbe&e=99ff097940)
.
Download Complete Call
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=6736f93b8e&e=99ff097940)
Back to Contents (#Contents)
** CALL FOR PAPERS:
------------------------------------------------------------
** 13th IEEE/ACM International Symposium on Networks-on-Chip
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=0f11ae78c5&e=99ff097940)
------------------------------------------------------------
**
------------------------------------------------------------
New York, USA (Co-located with Embedded Systems Week)
17-18 October 2019
The International Symposium on Networks-on-Chip (NOCS) is the premier event
dedicated to interdisciplinary research on on-chip, package-scale,
chip-to-chip, and datacenter rack-scale communication technology, architecture,
design methods, applications and systems. NOCS brings together scientists and
engineers working on network-on-chip (NoC) innovations and applications from
inter-related research communities, including discrete optimization and
algorithms, computer architecture, networking, circuits and systems, packaging,
embedded systems, and design automation. Topics of interest include, but are
not limited to: NoC Architecture and Implementation, Communication Analysis,
Optimization, & Verification, Novel NoC Technologies, NoC for Intelligent
Physical Systems, NoC at the Un-Core and System-level, Inter/Intra-Chip and
Rack-Scale Network.
Electronic paper submission requires a full paper, up to 8 double-column ACM
(sigconf) format pages, including figures and references. The program committee
will use a double-blind review process to evaluate papers based on scientific
merit, innovation, relevance, and presentation. Submitted papers must describe
original work that has not been published before or is under review by another
conference or journal at the same time. Each submission will be checked for any
significant similarity to previously published works or for simultaneous
submission to other archival venues, and such papers will be rejected.
Proposals for special sessions and demos are invited. Paper submissions and
demo proposals by industry researchers or engineers to share their experiences
and perspectives are also welcome. A percentage of accepted papers will be
recommended for publication in an IEEE journal after revision according to the
reviewers' comments. Please find the detailed submission instructions for paper
submission, special session, and demo proposals at the submission webpage
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=c93022bfd3&e=99ff097940)
.
Important Deadlines:
Abstract registration deadline: 10 May 2019
Full paper submission deadline: 17 May 2019
Notification of acceptance: 8 July 2019
Final version due: 22 July 2019
Download Complete Call
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=d3fef05f23&e=99ff097940)
Back to Contents (#Contents)
** CALL FOR PAPERS:
Design&Test Special Issue- Machine Intelligence at the Edge
------------------------------------------------------------
Recent years have seen widespread application of machine learning (ML) to a
diverse range of industries and problem domains. By taking advantage of the
availability of massive amounts of data and scalable compute resources, ML
methods -- including linear models (e.g., SVMs, logistic regression), decision
trees (e.g., XGBoost, lightGBM), and deep neural networks (e.g., CNNs and RNNs)
-- are able to outperform traditional hand-tuned models on today's large-scale
AI tasks. Due to their compute-intensive nature, machine learning systems are
typically deployed on clusters of CPUs/GPUs in public or private clouds.
However, the success of ML in sensing applications such as object detection and
speech recognition has also driven a demand for such technology (both training
and inference) in edge settings, for applications such as autonomous vehicles,
mobile devices, and embedded/IoT systems. Unfortunately, most existing ML
models, hardware, and frameworks are tailored towards a server environment
and are ill-equipped for edge computing.
Bringing ML to today's emerging edge applications involves tackling a diverse
set of challenges. To give just a few examples: power and energy requirements
for mobile, strict latency constraints for autonomous vehicles, security
concerns of model/data transmission for IoT, and intermittent operation for
embedded sensors. State-of-the-art ML systems in industry today already use
custom frameworks, algorithms, and hardware built for a server infrastructure.
Addressing the unique challenges of ML at the edge will similarly require
specialization, co-design, and integration of domain knowledge for the edge
across the computing stack.
Important Deadlines:
Submission Deadline: 1 March 2019
Notification First Round: 1 May 2019
Submission of Revision: 16 June 2019
Final Notification: 1 August 2019
Final Papers Due: 1 September 2019
More information can be found here
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=061260d8fb&e=99ff097940)
.
Download Complete Call
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=5172bfa2cd&e=99ff097940)
Back to Contents (#Contents)
** CALL FOR PAPERS:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Special Issue- Ferroelectric Transistors for Advanced Logic, Analog, and Memory
Applications
------------------------------------------------------------
Aims and Scope-
With recent advancements in the growth and processing of ferroelectric
materials and the emergence of CMOS compatible ferroelectrics, major research
and development efforts are underway on ferroelectric transistors for logic,
analog, and memory applications. With CMOS scaling facing challenges in
improving energy efficiency and power density, research in this area is needed
to augment the CMOS technology by lowering the required supply voltage or
adding new features and functionalities, such as non-volatility or
reconfigurability. Ferroelectric transistors also show great promise for
non-traditional circuits, such as convolutional and spiking neural networks and
in-memory computing. Research in this area spans many levels of abstraction:
from fundamental physical properties and material processing and
characterization, to various device concepts, and to circuit and system design
and benchmarking.
This special issue of the IEEE JXCDC will present the most recent developments
in the area of ferroelectric transistors based on experiments and theoretical
models. It aims to feature original papers on various aspects of this emerging
technology, its challenges and opportunities, its intrinsic versus practical
limits, and the circuits and systems it may enable.
Important Dates:
Open for Submission: 15 February 2019
Submission Deadline: 30 April 2019
First Notification: 15 May 2019
Revision Submission: 15 June 2019
Final Decision: 15 July 2019
Publication Online: 1 August 2019
Download Complete Call
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=891a9124d2&e=99ff097940)
Back to Contents (#Contents)
We thank you for forwarding this content
(http://us7.forward-to-friend.com/forward?u=a56289c418698825973a992ba&id=b638d41d4d&e=99ff097940)
to others who might be interested,
including other members of your group or organization.
https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=6ef404de61&e=99ff097940
Follow us on Twitter
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=2a9600612c&e=99ff097940)
https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=4d6e28a9fe&e=99ff097940
IEEE CEDA Website
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=d9656e2228&e=99ff097940)
https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=55f7146a37&e=99ff097940
Facebook Page
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=af19f05e76&e=99ff097940)
============================================================
Copyright © 2019 IEEE Council on Electronic Design Automation, All rights
reserved.
CEDA Currents is a publication of IEEE CEDA.
Please send contributions to the CEDA VP of Publicity, Vasilis F. Pavlidis (**
contribution form
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=810b71a5ea&e=99ff097940)
** )
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=d56625805f&e=99ff097940)
** unsubscribe from this list
(https://ieee-ceda.us7.list-manage.com/unsubscribe?u=a56289c418698825973a992ba&id=24229fc404&e=99ff097940&c=b638d41d4d)
** Update your profile and preferences now
(https://ieee-ceda.us7.list-manage.com/profile?u=a56289c418698825973a992ba&id=24229fc404&e=99ff097940)
** IEEE Privacy Policy
(https://ieee-ceda.us7.list-manage.com/track/click?u=a56289c418698825973a992ba&id=44f2217972&e=99ff097940)
_______________________________________________
uai mailing list
uai@ENGR.ORST.EDU
https://secure.engr.oregonstate.edu/mailman/listinfo/uai
